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1. 发明授权

US08785287B2 Method to tune narrow width effect with raised S/D structure 有权
标题翻译：用提高的S / D结构调整窄宽度效应的方法
公开(公告)号：US08785287B2
公开(公告)日：2014-07-22
申请号：US12803754
申请日：2010-07-06
申请人： Chunshan Yin , Guangyu Huang , Elgin Quek , Jae Gon Lee , Kian Ming Tan
发明人： Chunshan Yin , Guangyu Huang , Elgin Quek , Jae Gon Lee , Kian Ming Tan
IPC分类号： H01L21/336 , H01L21/265
CPC分类号： H01L27/088 , H01L21/26586 , H01L29/0847 , H01L29/1033 , H01L29/1045 , H01L29/41783 , H01L29/6659 , H01L29/7848
摘要： A method (and semiconductor device) of fabricating a semiconductor device adjusts gate threshold (Vt) of a field effect transistor (FET) with raised source/drain (S/D) regions. A halo region is formed in a two-step process that includes implanting dopants using conventional implantation techniques and implanting dopants at a specific twist angle. The dopant concentration in the halo region near the active edge of the raised S/D regions is higher and extends deeper than the dopant concentration within the interior region of the raised S/D regions. As a result, Vt near the active edge region is adjusted and different from the Vt at the active center regions, thereby achieving same or similar Vt for a FET with different width.
摘要翻译：制造半导体器件的方法（和半导体器件）调节具有升高的源极/漏极（S / D）区域的场效应晶体管（FET）的栅极阈值（Vt）。以包括使用常规植入技术注入掺杂剂并以特定扭转角注入掺杂剂的两步工艺形成晕圈区域。在升高的S / D区域的有源边缘附近的卤素区域中的掺杂剂浓度更高并且比在凸起的S / D区域的内部区域内的掺杂剂浓度更深。结果，有源边缘区域附近的Vt被调节并且与有源中心区域处的Vt不同，从而为具有不同宽度的FET获得相同或相似的Vt。

2. 发明申请

US20120007180A1 FinFET with novel body contact for multiple Vt applications 有权
标题翻译： FinFET具有新的身体接触，适用于多种Vt应用
公开(公告)号：US20120007180A1
公开(公告)日：2012-01-12
申请号：US12803776
申请日：2010-07-06
申请人： Chunshan Yin , Kian Ming Tan , Jae Gon Lee
发明人： Chunshan Yin , Kian Ming Tan , Jae Gon Lee
IPC分类号： H01L27/12 , H01L21/84
CPC分类号： H01L29/785 , H01L29/66795
摘要： FinFET devices are formed with body contact structures enabling the fabrication of such devices having different gate threshold voltages (Vt). A body contact layer is formed to contact the gate electrode (contact) enabling a forward body bias and a reduction in Vt. Two example methods of fabrication (and resulting structures) are provided. In one method, the gate electrode (silicon-based) and body contact layer (silicon) are connected by growing epitaxy which merges the two structures forming electrical contact. In another method, a via is formed that intersects with the gate electrode (suitable conductive material) and body contact layer and is filled with conductive material to electrically connect the two structures. As a result, various FinFETs with different Vt can be fabricated for different applications.
摘要翻译： FinFET器件形成有能够制造具有不同栅极阈值电压（Vt）的这种器件的体接触结构。形成身体接触层以接触栅电极（接触），从而能够实现正向偏置和Vt的减小。提供了两种制造方法（和结果）。在一种方法中，栅电极（硅基）和体接触层（硅）通过生长的外延连接，该外延合并形成电接触的两个结构。在另一种方法中，形成与栅电极（合适的导电材料）和体接触层相交的通孔，并且填充有导电材料以电连接两个结构。因此，可以为不同的应用制造具有不同Vt的各种FinFET。

3. 发明授权

US08735984B2 FinFET with novel body contact for multiple Vt applications 有权
标题翻译： FinFET具有新的身体接触，适用于多种Vt应用
公开(公告)号：US08735984B2
公开(公告)日：2014-05-27
申请号：US12803776
申请日：2010-07-06
申请人： Chunshan Yin , Kian Ming Tan , Jae Gon Lee
发明人： Chunshan Yin , Kian Ming Tan , Jae Gon Lee
IPC分类号： H01L21/84 , H01L27/12
CPC分类号： H01L29/785 , H01L29/66795
摘要： FinFET devices are formed with body contact structures enabling the fabrication of such devices having different gate threshold voltages (Vt). A body contact layer is formed to contact the gate electrode (contact) enabling a forward body bias and a reduction in Vt. Two example methods of fabrication (and resulting structures) are provided. In one method, the gate electrode (silicon-based) and body contact layer (silicon) are connected by growing epitaxy which merges the two structures forming electrical contact. In another method, a via is formed that intersects with the gate electrode (suitable conductive material) and body contact layer and is filled with conductive material to electrically connect the two structures. As a result, various FinFETs with different Vt can be fabricated for different applications.
摘要翻译： FinFET器件形成有能够制造具有不同栅极阈值电压（Vt）的这种器件的体接触结构。形成身体接触层以接触栅电极（接触），从而能够实现正向偏置和Vt的减小。提供了两种制造方法（和结果）。在一种方法中，栅电极（硅基）和体接触层（硅）通过生长的外延连接，该外延合并形成电接触的两个结构。在另一种方法中，形成与栅电极（合适的导电材料）和体接触层相交的通孔，并且填充有导电材料以电连接两个结构。因此，可以为不同的应用制造具有不同Vt的各种FinFET。

4. 发明申请

US20120007185A1 Novel method to tune narrow width effect with raised S/D structure 有权
标题翻译：用提高的S / D结构调整窄宽度效应的新方法
公开(公告)号：US20120007185A1
公开(公告)日：2012-01-12
申请号：US12803754
申请日：2010-07-06
申请人： Chunshan Yin , Guangyu Huang , Elgin Quek , Jae Gon Lee , Kian Ming Tan
发明人： Chunshan Yin , Guangyu Huang , Elgin Quek , Jae Gon Lee , Kian Ming Tan
IPC分类号： H01L27/088 , H01L21/336
CPC分类号： H01L27/088 , H01L21/26586 , H01L29/0847 , H01L29/1033 , H01L29/1045 , H01L29/41783 , H01L29/6659 , H01L29/7848
摘要： A method (and semiconductor device) of fabricating a semiconductor device adjusts gate threshold (Vt) of a field effect transistor (FET) with raised source/drain (S/D) regions. A halo region is formed in a two-step process that includes implanting dopants using conventional implantation techniques and implanting dopants at a specific twist angle. The dopant concentration in the halo region near the active edge of the raised S/D regions is higher and extends deeper than the dopant concentration within the interior region of the raised S/D regions. As a result, Vt near the active edge region is adjusted and different from the Vt at the active center regions, thereby achieving same or similar Vt for a FET with different width.
摘要翻译：制造半导体器件的方法（和半导体器件）调节具有升高的源极/漏极（S / D）区域的场效应晶体管（FET）的栅极阈值（Vt）。以包括使用常规植入技术注入掺杂剂并以特定扭转角注入掺杂剂的两步工艺形成晕圈区域。在升高的S / D区域的有源边缘附近的卤素区域中的掺杂剂浓度更高并且比在凸起的S / D区域的内部区域内的掺杂剂浓度更深。结果，有源边缘区域附近的Vt被调节并且与有源中心区域处的Vt不同，从而为具有不同宽度的FET获得相同或相似的Vt。

5. 发明授权

US08633081B2 Modifying growth rate of a device layer 有权
标题翻译：修改设备层的增长速度
公开(公告)号：US08633081B2
公开(公告)日：2014-01-21
申请号：US12980376
申请日：2010-12-29
申请人： Chunshan Yin , Palanivel Balasubramaniam , Jae Gon Lee , Elgin Quek
发明人： Chunshan Yin , Palanivel Balasubramaniam , Jae Gon Lee , Elgin Quek
IPC分类号： H01L21/336
CPC分类号： H01L21/02238 , H01L21/02299 , H01L21/2822 , H01L21/76232
摘要： A device includes a substrate with a device region on which a transistor is formed. The device region includes active edge regions and an active center region which have different oxidation growth rates. A growth rate modifier (GRM) comprising dopants which modifies oxidation growth rate is employed to produce a gate oxide layer which has a uniform thickness. The GRM may enhance or retard the oxidation growth, depending on the type of dopants used. Fluorine dopants enhance oxidation growth rate while nitrogen dopants retard oxidation growth rate.
摘要翻译：一种器件包括具有其上形成有晶体管的器件区域的衬底。器件区域包括有效边缘区域和具有不同氧化生长速率的活性中心区域。使用包含修饰氧化生长速率的掺杂剂的生长速率调节剂（GRM）来制造具有均匀厚度的栅极氧化物层。取决于所使用的掺杂剂的类型，GRM可以增强或延缓氧化生长。氟掺杂剂增强氧化生长速率，而氮掺杂剂延缓氧化生长速率。

6. 发明申请

US20120119281A1 INTEGRATED CIRCUIT SYSTEM WITH BANDGAP MATERIAL AND METHOD OF MANUFACTURE THEREOF 有权
标题翻译：具有带状材料的集成电路系统及其制造方法
公开(公告)号：US20120119281A1
公开(公告)日：2012-05-17
申请号：US12947530
申请日：2010-11-16
申请人： Chung Foong Tan , Eng Huat Toh , Jae Gon Lee , Chunshan Yin , Lakshmi Bera
发明人： Chung Foong Tan , Eng Huat Toh , Jae Gon Lee , Chunshan Yin , Lakshmi Bera
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L29/7881 , H01L21/28273 , H01L29/42324 , H01L29/42328 , H01L29/66825
摘要： A method of manufacturing an integrated circuit system includes: providing a substrate having a channel region; forming a gate stack over a portion of the channel region with the gate stack having a floating gate for storing an electrical charge; forming a source recess in the substrate adjacent to the gate stack; and forming a source by layering a first bandgap material in the source recess.
摘要翻译：一种制造集成电路系统的方法包括：提供具有沟道区的衬底; 在所述沟道区的一部分上形成栅极堆叠，所述栅极堆叠具有用于存储电荷的浮动栅极; 在所述衬底中邻近所述栅极堆叠形成源极凹槽; 以及通过在源凹槽中层叠第一带隙材料来形成源。

7. 发明授权

US08446779B2 Non-volatile memory using pyramidal nanocrystals as electron storage elements 有权
标题翻译：使用金字塔纳米晶体作为电子存储元件的非易失性存储器
公开(公告)号：US08446779B2
公开(公告)日：2013-05-21
申请号：US12583486
申请日：2009-08-21
申请人： Elgin Quek , Chunshan Yin , Shyue Seng Tan , Jae Gon Lee , Chung Foong Tan
发明人： Elgin Quek , Chunshan Yin , Shyue Seng Tan , Jae Gon Lee , Chung Foong Tan
IPC分类号： G11C16/04 , H01L29/788
CPC分类号： H01L29/42324 , G11C16/0416 , G11C2216/06 , H01L21/28273 , H01L27/11521 , H01L29/42332
摘要： A non-volatile memory device includes a floating gate with pyramidal-shaped silicon nanocrystals as electron storage elements. Electrons tunnel from the pyramidal-shaped silicon nanocrystals through a gate oxide layer to a control gate of the non-volatile memory device. The pyramidal shape of each silicon nanocrystal concentrates an electrical field at its peak to facilitate electron tunneling. This allows an erase process to occur at a lower tunneling voltage and shorter tunneling time than that of prior art devices.
摘要翻译：非易失性存储器件包括具有金字塔形的硅纳米晶体作为电子存储元件的浮动栅极。电子从金字塔形的硅纳米晶体通过栅极氧化层隧穿到非易失性存储器件的控制栅极。每个硅纳米晶体的锥体形状在其峰值处集中电场以促进电子隧穿。这允许擦除过程发生在比现有技术的器件更低的隧道电压和更短的隧道时间。

8. 发明申请

US20120038009A1 Novel methods to reduce gate contact resistance for AC reff reduction 有权
标题翻译：降低栅极接触电阻的新方法
公开(公告)号：US20120038009A1
公开(公告)日：2012-02-16
申请号：US12806354
申请日：2010-08-11
申请人： Eng Huat Toh , Elgin Quek , Chunshan Yin , Chung Foong Tan , Jae Gon Lee
发明人： Eng Huat Toh , Elgin Quek , Chunshan Yin , Chung Foong Tan , Jae Gon Lee
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/28079 , H01L21/28088 , H01L21/28097 , H01L29/495 , H01L29/4966 , H01L29/4975 , H01L29/517
摘要： A method (and semiconductor device) of fabricating a semiconductor device provides a field effect transistor (FET) with reduced gate contact resistance (and series resistance) for improved device performance. An impurity is implanted or deposited in the gate stack in an impurity region between the metal gate electrode and the gate contact layer. An anneal process is performed that converts the impurity region into a segregation layer which lowers the schottky barrier height (SBH) of the interface between the metal gate electrode (e.g., silicide) and gate contact layer (e.g., amorphous silicon). This results in lower gate contact resistance and effectively lowers the device's AC Reff.
摘要翻译：制造半导体器件的方法（和半导体器件）提供具有降低的栅极接触电阻（和串联电阻）的场效应晶体管（FET），以提高器件性能。在金属栅极电极和栅极接触层之间的杂质区域中将杂质注入或沉积在栅极堆叠中。执行退火处理，其将杂质区域转换成偏析层，其降低金属栅电极（例如，硅化物）和栅极接触层（例如非晶硅）之间的界面的肖特基势垒高度（SBH）。这导致较低的栅极接触电阻并有效降低器件的AC Reff。

9. 发明授权

US08563386B2 Integrated circuit system with bandgap material and method of manufacture thereof 有权
标题翻译：具有带隙材料的集成电路系统及其制造方法
公开(公告)号：US08563386B2
公开(公告)日：2013-10-22
申请号：US12947530
申请日：2010-11-16
申请人： Chung Foong Tan , Eng Huat Toh , Jae Gon Lee , Chunshan Yin , Lakshmi Bera
发明人： Chung Foong Tan , Eng Huat Toh , Jae Gon Lee , Chunshan Yin , Lakshmi Bera
IPC分类号： H01L21/336
CPC分类号： H01L29/7881 , H01L21/28273 , H01L29/42324 , H01L29/42328 , H01L29/66825
摘要： A method of manufacturing an integrated circuit system includes: providing a substrate having a channel region; forming a gate stack over a portion of the channel region with the gate stack having a floating gate for storing an electrical charge; forming a source recess in the substrate adjacent to the gate stack; and forming a source by layering a first bandgap material in the source recess.
摘要翻译：一种制造集成电路系统的方法包括：提供具有沟道区的衬底; 在所述沟道区的一部分上形成栅极堆叠，所述栅极堆叠具有用于存储电荷的浮动栅极; 在所述衬底中邻近所述栅极堆叠形成源极凹槽; 以及通过在源凹槽中层叠第一带隙材料来形成源。

10. 发明申请

US20100258868A1 INTEGRATED CIRCUIT SYSTEM WITH A FLOATING DIELECTRIC REGION AND METHOD OF MANUFACTURE THEREOF 有权
标题翻译：具有浮动介质区域的集成电路系统及其制造方法
公开(公告)号：US20100258868A1
公开(公告)日：2010-10-14
申请号：US12422694
申请日：2009-04-13
申请人： Chunshan Yin , Lee Wee Teo , Chung Foong Tan , Jae Gon Lee
发明人： Chunshan Yin , Lee Wee Teo , Chung Foong Tan , Jae Gon Lee
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/66636 , H01L29/0653 , H01L29/165 , H01L29/665 , H01L29/6653 , H01L29/66537 , H01L29/6656 , H01L29/6659 , H01L29/66772 , H01L29/7833 , H01L29/7847 , H01L29/7848 , H01L29/78603 , H01L29/78621
摘要： A method of manufacture of an integrated circuit system includes: providing a second layer between a first layer and a third layer; forming an active device over the third layer; forming the third layer to form an island region underneath the active device; forming the second layer to form a floating second layer with an undercut beneath the island region; and depositing a fourth layer around the island region and the floating second layer.
摘要翻译：一种制造集成电路系统的方法包括：在第一层和第三层之间提供第二层; 在第三层上形成有源器件; 形成第三层以在有源器件下方形成岛状区域; 形成第二层以形成在岛区下方具有底切的浮动第二层; 以及围绕岛区域和浮动第二层沉积第四层。

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