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1. 发明申请

US20100118606A1 Methods of programming non-volatile memory devices and memory devices programmed thereby 有权
标题翻译：对由此编程的非易失性存储器件和存储器件进行编程的方法
公开(公告)号：US20100118606A1
公开(公告)日：2010-05-13
申请号：US12590701
申请日：2009-11-12
申请人： Jae Duk Lee , Soon Moon Jung , Jung Dal Choi
发明人： Jae Duk Lee , Soon Moon Jung , Jung Dal Choi
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/3418 , G11C16/3427
摘要： In a method of programming a non-volatile memory device, and in a device incorporating the same, the memory device includes: a plurality of memory cell transistors arranged in a plurality of transistor strings, wherein a transistor string includes a plurality of memory cell transistors arranged in series; a plurality of word lines, each word line connected to a corresponding memory cell transistor of each of the different transistor strings; and a plurality of bit lines, each bit line connected to one of the transistor strings. The method comprises: applying a first voltage to a selected word line corresponding to a selected memory cell transistor of a selected transistor string to be programmed; and applying a second voltage to a neighboring word line neighboring the selected word line and corresponding to a neighboring transistor of the selected transistor string, wherein the first voltage is greater than the second voltage, the application of the first and second voltages to the selected and neighboring word lines respectively causing electrons to be generated by an electric field formed between the neighboring transistor and the selected memory cell transistor, the electrons accelerating toward the selected memory cell transistor and injecting into a charge storage layer of the selected memory cell transistor.
摘要翻译：在一种编程非易失性存储器件的方法中，以及在其中包含该非易失性存储器件的器件中，存储器件包括：多个存储单元晶体管，被布置在多个晶体管串中，其中晶体管串包括多个存储单元晶体管串联排列多个字线，每个字线连接到每个不同晶体管串的对应存储单元晶体管; 和多个位线，每个位线连接到一个晶体管串。该方法包括：将第一电压施加到与要编程的所选晶体管串的选定存储单元晶体管相对应的选定字线; 以及将第二电压施加到与所选择的字线相邻并且对应于所选择的晶体管串的相邻晶体管的相邻字线，其中所述第一电压大于所述第二电压，将所述第一和第二电压施加到所选择的和分别使相邻的晶体管和选择的存储单元晶体管之间形成的电场产生电子的相邻字线，电子向所选择的存储单元晶体管加速并注入到所选择的存储单元晶体管的电荷存储层中。

2. 发明授权

US08248853B2 Methods of programming non-volatile flash memory devices by applying a higher voltage level to a selected word line than to a word line neighboring the selected word line 有权
标题翻译：通过对所选择的字线施加比毗邻所选字线的字线更高的电压电平来对非易失性闪存器件进行编程的方法
公开(公告)号：US08248853B2
公开(公告)日：2012-08-21
申请号：US12590701
申请日：2009-11-12
申请人： Jae Duk Lee , Soon Moon Jung , Jung Dal Choi
发明人： Jae Duk Lee , Soon Moon Jung , Jung Dal Choi
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C11/5628 , G11C16/0483 , G11C16/3418 , G11C16/3427
摘要： In a method of programming a non-volatile memory device, a first voltage is applied to a selected word line corresponding to a selected memory cell transistor of a selected transistor string to be programmed; a second voltage is applied to a neighboring word line neighboring the selected word line and corresponding to a neighboring transistor of the selected transistor string, wherein the first voltage is greater than the second voltage, the application of the first and second voltages to the selected and neighboring word lines respectively causing electrons to be generated by an electric field formed between the neighboring transistor and the selected memory cell transistor, the electrons accelerating toward the selected memory cell transistor and injecting into a charge storage layer of the selected memory cell transistor; wherein the neighboring transistor is positioned between the selected memory cell transistor and one of a ground select transistor and a string select transistor, and the first voltage is applied to unselected word lines corresponding to unselected memory cell transistors of the selected transistor string positioned between the selected memory cell transistor and the other of the ground select transistor and the string select transistor.
摘要翻译：在编程非易失性存储器件的方法中，将第一电压施加到对应于要编程的所选择的晶体管串的选定存储单元晶体管的选定字线; 第二电压被施加到与所选择的字线相邻并且对应于所选择的晶体管串的相邻晶体管的相邻字线，其中第一电压大于第二电压，将第一和第二电压施加到所选择的和分别使相邻的晶体管与所选择的存储单元晶体管之间形成的电场产生电子的相邻字线，电子向所选择的存储单元晶体管加速并注入到所选存储单元晶体管的电荷存储层中; 其中所述相邻晶体管位于所选择的存储单元晶体管和接地选择晶体管和串选择晶体管中的一个之间，并且所述第一电压被施加到对应于所选择的晶体管串的未选择存储单元晶体管的未选择字线，存储单元晶体管和另一个接地选择晶体管和串选择晶体管。

3. 发明授权

US08540454B2 Manhole cover 失效
标题翻译：人孔盖
公开(公告)号：US08540454B2
公开(公告)日：2013-09-24
申请号：US13143085
申请日：2009-12-29
申请人： Jae Duk Lee
发明人： Jae Duk Lee
IPC分类号： E02D29/12
CPC分类号： E02D29/14
摘要： A manhole cover which has an upper body and a lower body coupled to each other to maintain balance, to endure loads applied from an external source in a stable manner, to protect the inside of the manhole from the ingress of rainwater, and to enable the upper body to be stably fixed inside the lower body.
摘要翻译：一种井盖，其具有彼此联接以保持平衡的上主体和下体，以以稳定的方式承受从外部源施加的载荷，以保护人孔内部免受雨水的侵入，并且使得上身稳定地固定在下身内。

4. 发明授权

US5733433A Heat generating type ink-jet print head 失效
公开(公告)号：US5733433A
公开(公告)日：1998-03-31
申请号：US475536
申请日：1995-06-07
申请人： Ho Jun Lee , Hi Deok Lee , Jae Duk Lee , Jun Bo Yoon , Ki Ho Han , Jae Kwan Kim , Chul Hi Han , Choong Ki Kim , Doo Won Seo
发明人： Ho Jun Lee , Hi Deok Lee , Jae Duk Lee , Jun Bo Yoon , Ki Ho Han , Jae Kwan Kim , Chul Hi Han , Choong Ki Kim , Doo Won Seo
IPC分类号： B41J2/05 , B41J2/14 , B41J2/16 , C25F3/14 , C25F3/16
CPC分类号： B41J2/14129 , B41J2/1603 , B41J2/1626 , B41J2/1632 , B41J2/1639 , B41J2/1642 , B41J2/1643 , B41J2/1646 , B41J2202/13
摘要： A heat generating type ink-jet print head including an ink supply passage for receiving an ink from an ink container, a micro chamber for storing the ink and nozzles, all being directly formed on a substrate, and a method for fabricating the ink-jet print head using an electrolytic polishing process, and a method for fabricating the ink-jet print head. The ink-jet print head is fabricated using an electrolytic polishing process, thereby achieving an accurate and inexpensive fabrication.

5. 发明申请

US20150132915A1 Non-Volatile Memory Devices and Manufacturing Methods Thereof 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20150132915A1
公开(公告)日：2015-05-14
申请号：US14457220
申请日：2014-08-12
申请人： Jin Taek Park , Young Woo Park , Jae Duk Lee
发明人： Jin Taek Park , Young Woo Park , Jae Duk Lee
IPC分类号： H01L29/66 , H01L27/115
CPC分类号： H01L29/513 , G11C16/0483 , H01L21/28273 , H01L27/11556 , H01L27/11582 , H01L29/42324 , H01L29/4234 , H01L29/42364 , H01L29/4916 , H01L29/66825 , H01L29/66833 , H01L29/7789 , H01L29/7926
摘要： There is provided a method of manufacturing a non-volatile memory device including: alternatively stacking a plurality of insulating layers and a plurality of conductive layers on a top surface of a substrate; forming an opening that exposes the top surface of the substrate and lateral surfaces of the insulating layers and the conductive layers; forming an anti-oxidation layer on at least the exposed lateral surfaces of the conductive layers; forming a gate dielectric layer on the anti-oxidation layer, the gate dielectric layer including a blocking layer, an electric charge storage layer, and a tunneling layer that are sequentially formed on the anti-oxidation layer; and forming a channel region on the tunneling layer
摘要翻译：提供了一种制造非易失性存储器件的方法，包括：在衬底的顶表面上交替堆叠多个绝缘层和多个导电层; 形成露出所述基板的顶表面和所述绝缘层和所述导电层的侧表面的开口; 在所述导电层的至少暴露的侧表面上形成抗氧化层; 在所述抗氧化层上形成栅介电层，所述栅极介电层包括依次形成在所述抗氧化层上的阻挡层，电荷存储层和隧穿层; 以及在隧道层上形成沟道区

6. 外观设计

USD931015S1 Bed frame 有权
公开(公告)号：USD931015S1
公开(公告)日：2021-09-21
申请号：US29696147
申请日：2019-06-25
申请人： Jae Duk Lee
设计人： Jae Duk Lee

7. 发明授权

US10115799B2 Non-volatile memory devices and manufacturing methods thereof 有权
公开(公告)号：US10115799B2
公开(公告)日：2018-10-30
申请号：US15408017
申请日：2017-01-17
申请人： Jin Taek Park , Young Woo Park , Jae Duk Lee
发明人： Jin Taek Park , Young Woo Park , Jae Duk Lee
IPC分类号： H01L29/51 , H01L29/66 , H01L29/778 , H01L29/792 , H01L27/11556 , H01L27/11582 , G11C16/04 , H01L21/28 , H01L29/423 , H01L29/49
摘要： There is provided a method of manufacturing a non-volatile memory device including: alternatively stacking a plurality of insulating layers and a plurality of conductive layers on a top surface of a substrate; forming an opening that exposes the top surface of the substrate and lateral surfaces of the insulating layers and the conductive layers; forming an anti-oxidation layer on at least the exposed lateral surfaces of the conductive layers; forming a gate dielectric layer on the anti-oxidation layer, the gate dielectric layer including a blocking layer, an electric charge storage layer, and a tunneling layer that are sequentially formed on the anti-oxidation layer; and forming a channel region on the tunneling layer.

8. 发明授权

US09564519B2 Non-volatile memory devices and manufacturing methods thereof 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US09564519B2
公开(公告)日：2017-02-07
申请号：US14457220
申请日：2014-08-12
申请人： Jin Taek Park , Young Woo Park , Jae Duk Lee
发明人： Jin Taek Park , Young Woo Park , Jae Duk Lee
IPC分类号： H01L29/66 , H01L29/778 , H01L29/792 , H01L27/115 , G11C16/04
CPC分类号： H01L29/513 , G11C16/0483 , H01L21/28273 , H01L27/11556 , H01L27/11582 , H01L29/42324 , H01L29/4234 , H01L29/42364 , H01L29/4916 , H01L29/66825 , H01L29/66833 , H01L29/7789 , H01L29/7926
摘要： There is provided a method of manufacturing a non-volatile memory device including: alternatively stacking a plurality of insulating layers and a plurality of conductive layers on a top surface of a substrate; forming an opening that exposes the top surface of the substrate and lateral surfaces of the insulating layers and the conductive layers; forming an anti-oxidation layer on at least the exposed lateral surfaces of the conductive layers; forming a gate dielectric layer on the anti-oxidation layer, the gate dielectric layer including a blocking layer, an electric charge storage layer, and a tunneling layer that are sequentially formed on the anti-oxidation layer; and forming a channel region on the tunneling layer.
摘要翻译：提供了一种制造非易失性存储器件的方法，包括：在衬底的顶表面上交替堆叠多个绝缘层和多个导电层; 形成露出所述基板的顶表面和所述绝缘层和所述导电层的侧表面的开口; 在所述导电层的至少暴露的侧表面上形成抗氧化层; 在所述抗氧化层上形成栅介电层，所述栅极介电层包括依次形成在所述抗氧化层上的阻挡层，电荷存储层和隧穿层; 以及在隧道层上形成沟道区。

9. 发明申请

US20110268501A1 MANHOLE COVER 失效
标题翻译：男子封面
公开(公告)号：US20110268501A1
公开(公告)日：2011-11-03
申请号：US13143085
申请日：2009-12-29
申请人： Jae Duk Lee
发明人： Jae Duk Lee
IPC分类号： E02D29/14
CPC分类号： E02D29/14
摘要： The present invention relates to a manhole cover which has an upper body and a lower body coupled to each other to maintain balance, to endure loads applied from an external source in a stable manner, to protect the inside of the manhole from the ingress of rainwater, and to enable the upper body to be stably fixed inside the lower body. To accomplish the above-described aim, the key technical features of the present invention relate to a manhole cover, comprising: a lower body, the inside of which is hollow, with a spiral rib formed along the inner surface of the hollow space, and a convex-concave portion formed on the upper surface of the spiral rib; an upper body which is coupled inside the lower body, and the inside of which is hollow, with a spiral rib and a convex-concave portion formed along the outer surface thereof to correspond to the spiral rib and the convex-concave portion of the lower body, and a stepped portion formed at the upper surface thereof; a cover mounted in the stepped portion of the upper body to protect the inside of the upper body from the introduction of foreign objects; and a waterproofing means removably arranged inside the upper body to protect the inside of the manhole from the ingress of rainwater.
摘要翻译：本发明涉及一种人孔盖，其具有彼此联接以保持平衡的上主体和下体，以稳定地承受从外部源施加的载荷，以保护人孔内部免受雨水的侵入并且能够使上身稳定地固定在下身内。为了实现上述目的，本发明的关键技术特征涉及一种人孔盖，包括：下体，其内部为中空，沿着中空空间的内表面形成螺旋肋，以及形成在所述螺旋肋的上表面上的凸凹部; 上体，其联接在下体内部，其内部为中空的，具有沿其外表面形成的螺旋肋和凸凹部，以对应于螺旋肋和下部的凸凹部主体和形成在其上表面的台阶部分; 安装在上身的阶梯部分中的盖子，用于保护上身的内部不引入异物; 以及可拆卸地布置在上身内部的防水装置，以保护人孔内部免受雨水的侵入。

10. 发明授权

US09887208B2 Vertical memory device 有权
公开(公告)号：US09887208B2
公开(公告)日：2018-02-06
申请号：US15218421
申请日：2016-07-25
申请人： Young Hwan Son , Young Woo Park , Jae Duk Lee
发明人： Young Hwan Son , Young Woo Park , Jae Duk Lee
IPC分类号： H01L27/115 , H01L27/11582 , H01L27/11573 , G11C16/04 , G11C16/26 , G11C16/10 , H01L27/11565 , H01L27/1157 , H01L27/11575
CPC分类号： H01L27/11582 , G11C16/0466 , G11C16/10 , G11C16/26 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L27/11575
摘要： A memory device may include a peripheral region and a cell region. The peripheral region may include a first substrate, a plurality of circuit elements disposed on the first substrate, a first insulating layer disposed on the plurality of circuit elements, and a first protective layer disposed in the first insulating layer. The cell region may include a second substrate disposed on the first insulating layer, wherein the cell region includes a first impurity region, a channel region extending in a direction substantially perpendicular to an upper surface of the second substrate, a plurality of gate electrode layers stacked on the second substrate and adjacent to the channel region, and a first contact electrically connected to the first impurity region, wherein the first protective layer is disposed below the first impurity region, and has a shape corresponding to a shape of the first impurity region.

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