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1. 发明授权

US5877791A Heat generating type ink-jet print head 失效
标题翻译：发热型喷墨打印头
公开(公告)号：US5877791A
公开(公告)日：1999-03-02
申请号：US763421
申请日：1996-12-11
申请人： Ho Jun Lee , Hi Deok Lee , Jae Duk Lee , Jun Bo Yoon , Ki Ho Han , Jae Kwan Kim , Chul Hi Han , Choong Ki Kim , Doo Won Seo
发明人： Ho Jun Lee , Hi Deok Lee , Jae Duk Lee , Jun Bo Yoon , Ki Ho Han , Jae Kwan Kim , Chul Hi Han , Choong Ki Kim , Doo Won Seo
IPC分类号： B41J2/05 , B41J2/14 , B41J2/16 , B41J2/135 , B41J2/145
CPC分类号： B41J2/14129 , B41J2/1603 , B41J2/1626 , B41J2/1632 , B41J2/1639 , B41J2/1642 , B41J2/1643 , B41J2/1646 , B41J2202/13
摘要： A heat generating type ink-jet print head including an ink supply passage for receiving an ink from an ink container, a micro chamber for storing the ink and nozzles, all being directly formed on a substrate, and a method for fabricating the ink-jet print head using an electrolytic polishing process, and a method for fabricating the ink-jet print head. The ink-jet print head is fabricated using an electrolytic polishing process, thereby achieving an accurate and inexpensive fabrication.
摘要翻译：一种发热型喷墨打印头，包括用于从墨水容器接收墨水的墨水供应通道，用于存储墨水的喷嘴和全部直接形成在基材上的喷嘴，以及用于制造喷墨的方法使用电解抛光工艺的打印头以及用于制造喷墨打印头的方法。使用电解抛光工艺制造喷墨打印头，从而实现精确和廉价的制造。

2. 发明授权

US5733433A Heat generating type ink-jet print head 失效
公开(公告)号：US5733433A
公开(公告)日：1998-03-31
申请号：US475536
申请日：1995-06-07
申请人： Ho Jun Lee , Hi Deok Lee , Jae Duk Lee , Jun Bo Yoon , Ki Ho Han , Jae Kwan Kim , Chul Hi Han , Choong Ki Kim , Doo Won Seo
发明人： Ho Jun Lee , Hi Deok Lee , Jae Duk Lee , Jun Bo Yoon , Ki Ho Han , Jae Kwan Kim , Chul Hi Han , Choong Ki Kim , Doo Won Seo
IPC分类号： B41J2/05 , B41J2/14 , B41J2/16 , C25F3/14 , C25F3/16
CPC分类号： B41J2/14129 , B41J2/1603 , B41J2/1626 , B41J2/1632 , B41J2/1639 , B41J2/1642 , B41J2/1643 , B41J2/1646 , B41J2202/13
摘要： A heat generating type ink-jet print head including an ink supply passage for receiving an ink from an ink container, a micro chamber for storing the ink and nozzles, all being directly formed on a substrate, and a method for fabricating the ink-jet print head using an electrolytic polishing process, and a method for fabricating the ink-jet print head. The ink-jet print head is fabricated using an electrolytic polishing process, thereby achieving an accurate and inexpensive fabrication.

3. 发明授权

US06586306B2 Method for fabricating semiconductor device 有权
公开(公告)号：US06586306B2
公开(公告)日：2003-07-01
申请号：US10125271
申请日：2002-04-18
申请人： Hi Deok Lee , Seong Hyung Park
发明人： Hi Deok Lee , Seong Hyung Park
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L29/665 , H01L29/7833
摘要： A method for fabricating a semiconductor device is disclosed. In a high speed device structure consisting of a salicide, in order to fabricate a device having at least two gate oxide structures in the identical chip, an LDD region of a core device region is formed, and an ion implant process for forming the LDD region of an input/output device region having a thick gate oxide and a process for forming a source/drain region at the rim of a field oxide of the core device region having a thin gate oxide are performed at the same time, thereby increasing a depth of a junction region. Thus, the junction leakage current is decreased in the junction region of the peripheral circuit region, and the process is simplified. As a result, a process yield and reliability of the device are improved.

4. 发明授权

US06562686B2 Method for fabricating semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US06562686B2
公开(公告)日：2003-05-13
申请号：US10083187
申请日：2002-02-26
申请人： Hi Deok Lee
发明人： Hi Deok Lee
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L29/665 , H01L29/66628 , H01L29/7834 , Y10S438/918
摘要： A method for fabricating a semiconductor device employing a salicide (self-aligned silicide) structure is disclosed. The method prevents a junction leakage current from being increased at a portion of a source/drain region which is adjacent to an field oxide, by forming the source/drain region comprised of a relatively deep SID region and a relatively shallow SID region, wherein the deep SID region is formed adjacent to the field oxide and the shallow SID region is formed adjacent to the insulating film spacer. The method comprises the steps of forming a field oxide in a semiconductor substrate, forming a gate oxide and a gate electrode on the semiconductor substrate, forming an LDD region in the semiconductor substrate along a side of the gate electrode, forming a sidewall spacer on each sidewall of the gate electrode, forming a protection layer pattern covering the field oxide and a portion of the LDD region, forming a SEG layer where the protection layer pattern is not covered, removing the protection layer pattern to expose the portion of the LDD region, forming a source/drain region comprised of a deep SID region and a shallow SID region, forming a silicide layer on the gate electrode, the SEG layer and the deep SID region.
摘要翻译：公开了一种制造采用硅化物（自对准硅化物）结构的半导体器件的方法。该方法通过形成由相对较深的SID区域和相对较浅的SID区域构成的源极/漏极区域来防止在与场氧化物相邻的源极/漏极区域的部分处增加结漏电流，其中，形成与场氧化物相邻的深SID区域，并且与绝缘膜间隔物相邻形成浅的SID区域。该方法包括以下步骤：在半导体衬底中形成场氧化物，在半导体衬底上形成栅极氧化物和栅电极，沿半导体衬底沿着栅电极侧形成LDD区，形成覆盖场氧化物的保护层图案和LDD区域的一部分，形成保护层图案未被覆盖的SEG层，去除保护层图案以露出LDD区域的部分，形成由深SID区域和浅SID区域构成的源极/漏极区域，在栅电极，SEG层和深SID区域上形成硅化物层。

5. 发明授权

US06548870B1 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US06548870B1
公开(公告)日：2003-04-15
申请号：US09723222
申请日：2000-11-28
申请人： Hi Deok Lee
发明人： Hi Deok Lee
IPC分类号： H01L2976
CPC分类号： H01L29/42372 , H01L21/82345 , H01L29/66484 , H01L29/7831
摘要： In the semiconductor device, a first impurity region and a second impurity region are formed in a surface of a semiconductor substrate at a regular interval, and a gate insulating layer is formed on the semiconductor substrate between the first impurity region and the second impurity region. At least two gate electrodes are formed on the gate insulating layer, and are insulated from one another by an intergate insulation layer.
摘要翻译：在半导体器件中，在半导体衬底的表面中以规则的间隔形成第一杂质区和第二杂质区，并且在半导体衬底上在第一杂质区和第二杂质区之间形成栅极绝缘层。在栅极绝缘层上形成至少两个栅电极，并通过栅间绝缘层彼此绝缘。

6. 发明授权

US06709939B2 Method for fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US06709939B2
公开(公告)日：2004-03-23
申请号：US10409964
申请日：2003-04-09
申请人： Hi Deok Lee , Seong Hyung Park
发明人： Hi Deok Lee , Seong Hyung Park
IPC分类号： H01L21336
CPC分类号： H01L29/6659 , H01L29/665 , H01L29/7833
摘要： A method for fabricating a semiconductor device is disclosed. In a high speed device structure consisting of a salicide, in order to fabricate a device having at least two gate oxide structures in the identical chip, an LDD region of a core device region is formed, and an ion implant process for forming the LDD region of an input/output device region having a thick gate oxide and a process for forming a source/drain region at the rim of a field oxide of the core device region having a thin gate oxide are performed at the same time, thereby increasing a depth of a junction region. Thus, the junction leakage current is decreased in the junction region of the peripheral circuit region, and the process is simplified. As a result, a process yield and reliability of the device are improved.
摘要翻译：公开了一种制造半导体器件的方法。在由自对准硅化物组成的高速装置结构中，为了制造在同一芯片中具有至少两个栅极氧化物结构的器件，形成芯部器件区域的LDD区域，形成LDD区域的离子注入工艺具有厚栅极氧化物的输入/输出器件区域和用于在具有薄栅极氧化物的芯器件区域的场氧化物的边缘处形成源极/漏极区域的工艺同时进行，从而增加深度的连接区域。因此，在外围电路区域的结区域中结漏电流减小，并且处理简化。结果，改善了设备的工艺成品率和可靠性。

7. 发明授权

US07605068B2 Semiconductor device having a silicide layer and manufacturing method thereof 有权
标题翻译：具有硅化物层的半导体器件及其制造方法
公开(公告)号：US07605068B2
公开(公告)日：2009-10-20
申请号：US11345265
申请日：2006-01-31
申请人： Chel Jong Choi , Yong Jin Kim , Hi Deok Lee
发明人： Chel Jong Choi , Yong Jin Kim , Hi Deok Lee
IPC分类号： H01L21/3205 , H01L21/44
CPC分类号： H01L29/7833 , H01L21/28518 , H01L29/665 , H01L29/6659
摘要： Provided is a semiconductor device and a manufacturing method thereof. The method includes the steps of: forming a thin film transistor including a substrate having a semiconductor layer and silicon, a gate insulation layer formed on the semiconductor layer, a gate electrode formed on the gate insulation layer, and source and drain regions formed in the semiconductor layer; forming a first metal layer on the substrate having the semiconductor layer and the gate electrode; forming a second metal layer on the first metal layer; forming a third metal layer on the second metal layer; forming a nitride layer on the third metal layer; and annealing the substrate having the nitride layer, and forming a silicide layer on the gate electrode and the source and drain regions.
摘要翻译：提供一种半导体器件及其制造方法。该方法包括以下步骤：形成薄膜晶体管，其包括具有半导体层和硅的衬底，形成在半导体层上的栅极绝缘层，形成在栅极绝缘层上的栅极电极以及形成在栅极绝缘层中的源极和漏极区域半导体层; 在具有半导体层和栅电极的基板上形成第一金属层; 在所述第一金属层上形成第二金属层; 在所述第二金属层上形成第三金属层; 在所述第三金属层上形成氮化物层; 以及使具有氮化物层的衬底退火，以及在栅电极和源极和漏极区上形成硅化物层。

8. 发明授权

US06432783B1 Method for doping a semiconductor device through a mask 失效
标题翻译：通过掩模掺杂半导体器件的方法
公开(公告)号：US06432783B1
公开(公告)日：2002-08-13
申请号：US09722818
申请日：2000-11-28
申请人： Hi Deok Lee
发明人： Hi Deok Lee
IPC分类号： H01L21336
CPC分类号： H01L29/66575 , H01L21/266 , H01L21/28123 , H01L21/823842 , H01L21/823878 , H01L29/1041 , H01L29/4916 , Y10S438/914 , Y10S438/942
摘要： The manufacturing method produces a semiconductor in which current is not generated during the off state by reducing the electric field at the corner of an active region. The method includes patterning a gate material layer on a predetermined portion on the active region. The mask has an open region which exposes the active region but does not expose the filed region. A gate electrode and source/drain regions are formed by doping impurities into the exposed gate material layer and the active region.
摘要翻译：制造方法产生半导体，其中通过减少有源区域拐角处的电场而在断开状态期间不产生电流。该方法包括在有源区上的预定部分上形成栅极材料层。掩模具有暴露活性区域但不暴露归属区域的开放区域。通过将杂质掺杂到暴露的栅极材料层和有源区中来形成栅电极和源极/漏极区。

9. 发明授权

US06242937B1 Hot carrier measuring circuit 有权
标题翻译：热载体测量电路
公开(公告)号：US06242937B1
公开(公告)日：2001-06-05
申请号：US09306441
申请日：1999-05-06
申请人： Hi Deok Lee , Dae Mann Kim , Sang Gi Lee , Myoung Jun Jang
发明人： Hi Deok Lee , Dae Mann Kim , Sang Gi Lee , Myoung Jun Jang
IPC分类号： G01R3126
CPC分类号： G01R31/2849 , G01R31/2648
摘要： A hot carrier measuring circuit of the present invention, which measures the characteristic degradation of a semiconductor device due to AC operation, includes a pulse generator generating at least two pulse signals which are partially overlapped with each other and have various duty ratios, a level shifter shifting the pulse signal which are generated in the pulse generator to a desired voltage level, and a measuring device receiving the pulse signals outputted from the level shifter to at least one terminal thereof.
摘要翻译：测量由于交流运行而导致的半导体器件的特性劣化的本发明的热载流子测量电路包括产生彼此部分重叠并具有各种占空比的至少两个脉冲信号的脉冲发生器，电平转换器将在脉冲发生器中产生的脉冲信号移动到期望的电压电平;以及测量装置，将从电平移位器输出的脉冲信号接收到其至少一个端子。

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