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1. 发明申请

US20130264718A1 LAYOUT OF MEMORY STRAP CELL 有权
标题翻译：记忆层细胞的布局
公开(公告)号：US20130264718A1
公开(公告)日：2013-10-10
申请号：US13443467
申请日：2012-04-10
申请人： Jacklyn CHANG , Evan Yong ZHANG , Derek C. TAO , Kuoyuan (Peter) HSU
发明人： Jacklyn CHANG , Evan Yong ZHANG , Derek C. TAO , Kuoyuan (Peter) HSU
IPC分类号： H01L23/498
CPC分类号： H01L27/1104 , H01L27/0207
摘要： A layout structure includes a substrate, a well, a first dopant area, a second dopant area, a first poly region, a third dopant area, a fourth dopant area, and a second poly region. The well is in the substrate. The first poly region is in between the first dopant area and the second dopant area. The second poly region is in between the third dopant area and the fourth dopant area. The first dopant area, the second dopant area, the third dopant area, and the fourth dopant area are in the well. The first dopant area is configured to serve as a source of a transistor and to receive a first voltage value from a first power supply source. The well is configured to serve as a bulk of the transistor and to receive a second voltage value from a second power supply source.
摘要翻译：布局结构包括衬底，阱，第一掺杂区，第二掺杂区，第一多晶区，第三掺杂区，第四掺杂区和第二多晶区。井在底层。第一多晶硅区位于第一掺杂区和第二掺杂区之间。第二聚合区位于第三掺杂区和第四掺杂区之间。第一掺杂剂区域，第二掺杂剂区域，第三掺杂剂区域和第四掺杂剂区域在井中。第一掺杂剂区域被配置为用作晶体管的源极并且从第一电源接收第一电压值。阱被配置为用作晶体管的体积并从第二电源接收第二电压值。

2. 发明申请

US20130088925A1 LAYOUT OF MEMORY CELLS 有权
标题翻译：记忆细胞的布局
公开(公告)号：US20130088925A1
公开(公告)日：2013-04-11
申请号：US13267235
申请日：2011-10-06
申请人： Jacklyn CHANG , Derek C. TAO , Yukit TANG , Kuoyuan (Peter) HSU
发明人： Jacklyn CHANG , Derek C. TAO , Yukit TANG , Kuoyuan (Peter) HSU
IPC分类号： G11C7/10
CPC分类号： G11C7/18 , G11C11/412 , G11C11/413 , H01L27/0207 , H01L27/1104
摘要： A semiconductor structure includes a first strap cell, a first read port, and a first VSS terminal. The first strap cell has a first strap cell VSS region. The first read port has a first read port VSS region, a first read port read bit line region, and a first read port poly region. The first VSS terminal is configured to electrically couple the first strap cell VSS region and the first read port VSS region.
摘要翻译：半导体结构包括第一带状电池，第一读取端口和第一VSS端子。第一带状电池具有第一带电池VSS区域。第一读取端口具有第一读取端口VSS区域，第一读取端口读取位线区域和第一读取端口聚合区域。第一VSS端子被配置为电耦合第一带电池VSS区域和第一读取端口VSS区域。

3. 发明申请

US20130215693A1 TRACKING CAPACITIVE LOADS 有权
标题翻译：跟踪电容负载
公开(公告)号：US20130215693A1
公开(公告)日：2013-08-22
申请号：US13399877
申请日：2012-02-17
申请人： Derek C. TAO , Young Seog KIM , Kuoyuan (Peter) HSU , Bing WANG , Annie-Li-Keow LUM
发明人： Derek C. TAO , Young Seog KIM , Kuoyuan (Peter) HSU , Bing WANG , Annie-Li-Keow LUM
IPC分类号： G11C7/00
CPC分类号： G11C29/24 , G11C7/222 , G11C11/41 , G11C29/50012 , G11C2029/5002
摘要： A time delay is determined to cover a timing of a memory cell in a memory macro having a tracking circuit. Based on the time delay, a capacitance corresponding to the time delay is determined. A capacitor having the determined capacitance is utilized. The capacitor is coupled to a first data line of a tracking cell of the tracking circuit. A first transition of the first data line causes a first transition of a second data line of the memory cell.
摘要翻译：确定时间延迟以覆盖具有跟踪电路的存储器宏中的存储器单元的定时。基于时间延迟，确定与时间延迟相对应的电容。使用具有确定的电容的电容器。电容器耦合到跟踪电路的跟踪单元的第一数据线。第一数据线的第一转变导致存储器单元的第二数据线的第一转变。

4. 发明申请

US20140269026A1 TRACKING CIRCUIT 有权
标题翻译：跟踪电路
公开(公告)号：US20140269026A1
公开(公告)日：2014-09-18
申请号：US13840668
申请日：2013-03-15
申请人： Derek C. TAO , Annie-Li-Keow LUM , Kuoyuan (Peter) HSU
发明人： Derek C. TAO , Annie-Li-Keow LUM , Kuoyuan (Peter) HSU
IPC分类号： G11C7/22
CPC分类号： G11C7/227 , G11C11/419
摘要： A circuit is in a memory macro and comprises a write path, a read path, a selection circuit, and a clock generator circuit. The write path includes a first signal generated based on a first edge of a clock signal in a write operation of the memory macro. The read path includes a second signal generated based on a first edge of the clock signal in a read operation of the memory macro. The selection circuit is configured to select the first signal as a third signal in the write operation of the memory macro, and to select the second signal as the third signal in the read operation of the memory macro. The clock generator circuit is configured to generate a second edge of the clock signal in the write operation or in the read operation based on the third signal.
摘要翻译：电路位于存储器宏中，并且包括写入路径，读取路径，选择电路和时钟发生器电路。写入路径包括在存储器宏的写入操作中基于时钟信号的第一边缘生成的第一信号。读取路径包括在存储器宏的读取操作中基于时钟信号的第一边缘生成的第二信号。选择电路被配置为在存储器宏的写入操作中选择第一信号作为第三信号，并且在存储器宏的读取操作中选择第二信号作为第三信号。时钟发生器电路被配置为在写入操作或基于第三信号的读取操作中产生时钟信号的第二边沿。

5. 发明申请

US20120206983A1 TRACKING SCHEME FOR MEMORY 有权
标题翻译：记忆追踪方案
公开(公告)号：US20120206983A1
公开(公告)日：2012-08-16
申请号：US13026021
申请日：2011-02-11
申请人： Yong ZHANG , Derek C. TAO , Dongsik JEONG , Young Suk KIM , Kuoyuan (Peter) HSU
发明人： Yong ZHANG , Derek C. TAO , Dongsik JEONG , Young Suk KIM , Kuoyuan (Peter) HSU
IPC分类号： G11C7/06 , G11C7/00
CPC分类号： G11C7/227 , G11C11/419
摘要： A memory has a tracking circuit for a read tracking operation. The memory includes a memory bit cell array, a tracking column, a tracking row, a sense amplifier row coupled to the memory bit cell array and the tracking row, and a sense amplifier enable logic. The memory further includes a tracking bit line coupled to the tracking column and the sense amplifier enable logic, and a tracking word line coupled to the tracking row and the sense amplifier enable logic. The tracking circuit is configured to track a column time delay along the tracking column before a row time delay along the tracking row.
摘要翻译：存储器具有用于读取跟踪操作的跟踪电路。存储器包括存储位单元阵列，跟踪列，跟踪行，耦合到存储器位单元阵列和跟踪行的读出放大器行以及读出放大器使能逻辑。存储器还包括耦合到跟踪列和读出放大器使能逻辑的跟踪位线，以及耦合到跟踪行和读出放大器使能逻辑的跟踪字线。跟踪电路被配置为沿着跟踪行在行时间延迟之前跟踪沿着跟踪列的列时间延迟。

6. 发明申请

US20130088926A1 TRACKING MECHANISMS 有权
标题翻译：跟踪机制
公开(公告)号：US20130088926A1
公开(公告)日：2013-04-11
申请号：US13253749
申请日：2011-10-05
申请人： Derek C. TAO , Annie-Li-Keow LUM , Yukit TANG , Kuoyuan (Peter) HSU
发明人： Derek C. TAO , Annie-Li-Keow LUM , Yukit TANG , Kuoyuan (Peter) HSU
IPC分类号： G11C7/10 , G11C7/00
CPC分类号： G11C7/222 , G11C7/10 , G11C7/1051 , G11C11/419
摘要： A tracking edge of a tracking signal is activated. A buffer is turned off and a latching circuit is turned on, based on the tracking edge of the tracking signal. A buffer output of the buffer is coupled to a latch output of the latching circuit at a node. The buffer receives a data line of a memory macro.
摘要翻译：跟踪信号的跟踪边缘被激活。基于跟踪信号的跟踪边缘，缓冲器被关闭并且锁存电路被接通。缓冲器的缓冲器输出耦合到节点处的锁存电路的锁存器输出。缓冲区接收一个内存宏的数据行。

7. 发明申请

US20120182819A1 RECYCLING CHARGES 有权
标题翻译：回收费
公开(公告)号：US20120182819A1
公开(公告)日：2012-07-19
申请号：US13429082
申请日：2012-03-23
申请人： Young Seog KIM , Kuoyuan (Peter) HSU , Derek C. TAO , Young Suk KIM
发明人： Young Seog KIM , Kuoyuan (Peter) HSU , Derek C. TAO , Young Suk KIM
IPC分类号： G11C5/14 , G05F3/02
CPC分类号： G11C11/412
摘要： A circuit includes a first node; a second node; a first PMOS transistor having a source coupled to the first node, a drain coupled to a first control transistor, and a gate driven by a first voltage; and a first NMOS transistor having a source coupled to the second node, a drain coupled to the first control transistor, and a gate driven by a second voltage. The first PMOS transistor is configured to automatically turn off based on the first voltage and a first node voltage at the first node. The first NMOS transistor is configured to automatically turn off based on the second voltage and a second node voltage at the second node. When the first PMOS transistor, the control transistor, and the first NMOS transistor are on, the first node voltage is lowered while the second voltage is raised.
摘要翻译：电路包括第一节点; 第二个节点; 具有耦合到第一节点的源极的第一PMOS晶体管，耦合到第一控制晶体管的漏极和由第一电压驱动的栅极; 以及第一NMOS晶体管，其具有耦合到第二节点的源极，耦合到第一控制晶体管的漏极和由第二电压驱动的栅极。第一PMOS晶体管被配置为基于第一节点处的第一电压和第一节点电压自动关闭。第一NMOS晶体管被配置为基于第二节点处的第二电压和第二节点电压自动关闭。当第一PMOS晶体管，控制晶体管和第一NMOS晶体管导通时，第一节点电压降低，而第二电压升高。

8. 发明申请

US20120020169A1 TWO-PORT SRAM WRITE TRACKING SCHEME 有权
标题翻译：双端口SRAM写入跟踪方案
公开(公告)号：US20120020169A1
公开(公告)日：2012-01-26
申请号：US12839624
申请日：2010-07-20
申请人： Bing WANG , Kuoyuan (Peter) HSU , Derek C. TAO
发明人： Bing WANG , Kuoyuan (Peter) HSU , Derek C. TAO
IPC分类号： G11C7/10
CPC分类号： G11C11/419 , G11C11/413
摘要： A Static Random Access Memory (SRAM) includes at least two memory cells sharing a read bit line (RBL) and a write bit line (WBL). Each memory cell is coupled to a respective read word line (RWL) and a respective write word line (WWL). A write tracking control circuit is coupled to the memory cells for determining a write time of the memory cells. The write tracking control circuit is capable of receiving an input voltage and providing an output voltage. The respective RWL and the respective WWL of each memory cell are asserted during a write tracking operation.
摘要翻译：静态随机存取存储器（SRAM）包括共享读位线（RBL）和写位线（WBL）的至少两个存储器单元。每个存储单元耦合到相应的读字线（RWL）和相应的写字线（WWL）。写跟踪控制电路耦合到存储器单元，以确定存储器单元的写入时间。写跟踪控制电路能够接收输入电压并提供输出电压。在写跟踪操作期间，各存储单元的相应RWL和相应的WWL被断言。

9. 发明申请

US20120019312A1 RECYCLING CHARGES 有权
公开(公告)号：US20120019312A1
公开(公告)日：2012-01-26
申请号：US12843366
申请日：2010-07-26
申请人： Young Seog KIM , Kuoyuan (Peter) HSU , Derek C. TAO , Young Suk KIM
发明人： Young Seog KIM , Kuoyuan (Peter) HSU , Derek C. TAO , Young Suk KIM
IPC分类号： G05F3/02
CPC分类号： G11C11/412
摘要： A circuit includes a first node; a second node; a first PMOS transistor having a source coupled to the first node, a drain coupled to a first control transistor, and a gate driven by a first voltage; and a first NMOS transistor having a source coupled to the second node, a drain coupled to the first control transistor, and a gate driven by a second voltage. The first PMOS transistor is configured to automatically turn off based on the first voltage and a first node voltage at the first node. The first NMOS transistor is configured to automatically turn off based on the second voltage and a second node voltage at the second node. When the first PMOS transistor, the control transistor, and the first NMOS transistor are on, the first node voltage is lowered while the second voltage is raised.

10. 发明申请

US20120014201A1 DUAL RAIL MEMORY 有权
标题翻译：双轨记忆
公开(公告)号：US20120014201A1
公开(公告)日：2012-01-19
申请号：US12835197
申请日：2010-07-13
申请人： Derek C. TAO , Kuoyuan (Peter) HSU , Dong Sik JEONG , Young Suk KIM , Young Seog KIM , Yukit TANG
发明人： Derek C. TAO , Kuoyuan (Peter) HSU , Dong Sik JEONG , Young Suk KIM , Young Seog KIM , Yukit TANG
IPC分类号： G11C5/14
CPC分类号： G11C5/14
摘要： A memory comprising: a plurality of memory cells arranged in a plurality of rows and a plurality of columns. A column of the plurality of columns including a first power supply node configured to provide a first voltage, a second power supply node configured to provide a second voltage, a plurality of internal supply nodes electrically coupled together and configured to receive the first voltage or the second voltage for a plurality of memory cells in the column and a plurality of internal ground nodes. The internal ground nodes electrically coupled together and configured to provide at least two current paths for the plurality of memory cells in the column.
摘要翻译：一种存储器，包括：布置成多行和多列的多个存储单元。所述多列的列包括被配置为提供第一电压的第一电源节点，被配置为提供第二电压的第二电源节点，电耦合在一起并被配置为接收第一电压或该列中的多个存储单元的第二电压和多个内部接地节点。内部接地节点电耦合在一起并且被配置为为列中的多个存储器单元提供至少两个电流路径。

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