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1. 发明申请

US20120014201A1 DUAL RAIL MEMORY 有权
标题翻译：双轨记忆
公开(公告)号：US20120014201A1
公开(公告)日：2012-01-19
申请号：US12835197
申请日：2010-07-13
申请人： Derek C. TAO , Kuoyuan (Peter) HSU , Dong Sik JEONG , Young Suk KIM , Young Seog KIM , Yukit TANG
发明人： Derek C. TAO , Kuoyuan (Peter) HSU , Dong Sik JEONG , Young Suk KIM , Young Seog KIM , Yukit TANG
IPC分类号： G11C5/14
CPC分类号： G11C5/14
摘要： A memory comprising: a plurality of memory cells arranged in a plurality of rows and a plurality of columns. A column of the plurality of columns including a first power supply node configured to provide a first voltage, a second power supply node configured to provide a second voltage, a plurality of internal supply nodes electrically coupled together and configured to receive the first voltage or the second voltage for a plurality of memory cells in the column and a plurality of internal ground nodes. The internal ground nodes electrically coupled together and configured to provide at least two current paths for the plurality of memory cells in the column.
摘要翻译：一种存储器，包括：布置成多行和多列的多个存储单元。所述多列的列包括被配置为提供第一电压的第一电源节点，被配置为提供第二电压的第二电源节点，电耦合在一起并被配置为接收第一电压或该列中的多个存储单元的第二电压和多个内部接地节点。内部接地节点电耦合在一起并且被配置为为列中的多个存储器单元提供至少两个电流路径。

2. 发明授权

US5754418A High voltage generation circuit for semiconductor memory device 失效
标题翻译：用于半导体存储器件的高压发生电路
公开(公告)号：US5754418A
公开(公告)日：1998-05-19
申请号：US742682
申请日：1996-10-31
申请人： Jin Ho Park , Jae Ik Doh , Dong Sik Jeong
发明人： Jin Ho Park , Jae Ik Doh , Dong Sik Jeong
IPC分类号： G11C11/407 , G11C5/14 , G11C11/401 , G11C29/00 , G11C29/06 , H02M3/07 , H02M3/18 , G01R31/26 , G05F3/02 , G11C7/00
CPC分类号： G11C5/145 , G11C5/143
摘要： A high voltage generation circuit for a semiconductor memory device comprising a high voltage detector for detecting a high voltage, a ring oscillator for generating a pulse signal in response to an output signal from the high voltage detector when a power-up signal is made active, a high voltage pump circuit for performing a charge pumping operation to generate the high voltage and transfer the generated high voltage to a high voltage output terminal, and a pump controller for controlling the charge pumping operation of the high voltage pump circuit in response to the pulse signal from the ring oscillator. The high voltage generation circuit further comprises an operating voltage detector for detecting whether an external voltage from an external voltage source has an operating voltage level, a burn-in test voltage detector for detecting whether the external voltage from the external voltage source has a level higher than the operating voltage level, a switching circuit for transferring the external voltage from the external voltage source to the high voltage output terminal, and a driver for selectively driving the high voltage detector and the switching circuit in response to output signals from the operating voltage detector and burn-in test voltage detector.
摘要翻译：一种用于半导体存储器件的高电压产生电路，包括用于检测高电压的高电压检测器，响应于当上电信号有效时来自高电压检测器的输出信号产生脉冲信号的环形振荡器，用于执行电荷泵送操作以产生高电压并将所产生的高电压传送到高电压输出端子的高压泵电路，以及用于响应于脉冲控制高压泵电路的电荷泵送操作的泵控制器来自环形振荡器的信号。高压发生电路还包括用于检测来自外部电压源的外部电压是否具有工作电压电平的工作电压检测器，用于检测来自外部电压源的外部电压是否具有较高电平的老化测试电压检测器用于将来自外部电压源的外部电压传送到高电压输出端子的开关电路以及用于响应于来自工作电压检测器的输出信号选择性地驱动高电压检测器和开关电路的驱动器和老化测试电压检测器。

3. 发明授权

US09899312B2 Isolating electric paths in semiconductor device packages 有权
公开(公告)号：US09899312B2
公开(公告)日：2018-02-20
申请号：US11403626
申请日：2006-04-13
申请人： Adrian E. Ong , Dong Sik Jeong
发明人： Adrian E. Ong , Dong Sik Jeong
IPC分类号： H01L23/58 , H01L29/10 , H01L23/50 , H01L21/48 , H01L23/538
CPC分类号： H01L23/50 , H01L21/485 , H01L23/5382 , H01L2924/0002 , H01L2924/00
摘要： Methods, systems, and apparatus for reducing power consumption or signal distortions in a semiconductor device package. The semiconductor device package includes a semiconductor device, a first electric path, a second electric path, and an isolation element in the first electric path. The second electric path is electrically connected to the first electric path and a functional unit of the device. The isolation element separates an isolated portion in the first electric path from the second electric path, where the isolation element is configured to reduce current in the isolated portion when a signal is passing through the second electric path.

4. 发明授权

US08305827B2 Dual rail memory 有权
标题翻译：双轨内存
公开(公告)号：US08305827B2
公开(公告)日：2012-11-06
申请号：US12835197
申请日：2010-07-13
申请人： Derek C. Tao , Kuoyuan (Peter) Hsu , Dong Sik Jeong , Young Suk Kim , Young Seog Kim , Yukit Tang
发明人： Derek C. Tao , Kuoyuan (Peter) Hsu , Dong Sik Jeong , Young Suk Kim , Young Seog Kim , Yukit Tang
IPC分类号： G11C5/14
CPC分类号： G11C5/14
摘要： A memory array comprises a plurality of memory cells arranged in a plurality of rows and a plurality of columns. A column of the plurality of columns includes a first power supply node configured to provide a first voltage, a second power supply node configured to provide a second voltage, and a plurality of internal supply nodes electrically coupled together and configured to receive the first voltage or the second voltage for a plurality of memory cells in the column and a plurality of internal ground nodes. The internal ground nodes are electrically coupled together and configured to provide at least two current paths for the plurality of memory cells in the column.
摘要翻译：存储器阵列包括以多行和多列布置的多个存储单元。多列的列包括被配置为提供第一电压的第一电源节点，被配置为提供第二电压的第二电源节点和电耦合在一起并被配置为接收第一电压的多个内部供电节点，该列中的多个存储单元的第二电压和多个内部接地节点。内部接地节点电耦合在一起并且被配置为为列中的多个存储器单元提供至少两个电流路径。

5. 发明授权

US06288947B1 Data output apparatus guaranteeing complete data transfer using delayed time in memory device having pipelatch circuits 有权
标题翻译：数据输出装置保证在具有管线电路的存储器件中使用延迟时间完成数据传输
公开(公告)号：US06288947B1
公开(公告)日：2001-09-11
申请号：US09604687
申请日：2000-06-27
申请人： Kwan-Weon Kim , Dong-Sik Jeong
发明人： Kwan-Weon Kim , Dong-Sik Jeong
IPC分类号： G11C710
CPC分类号： G11C7/106 , G11C7/1006 , G11C7/1039 , G11C7/1051 , G11C7/1066 , G11C7/1072 , G11C11/4093 , G11C11/4096
摘要： A memory device having a plurality of pipelatch circuits storing data from memory cells via global input/output lines, a pipelatch input control circuit to selectively couple the pipelatch circuit to the global input/output lines in response to a pipelatch control signal, and a pipe count signal generator to control a data path between the pipelatch circuits and an output driver, wherein the pipelatch input control circuit includes: a first control signal generator receiving a first control signal and global input/output line signals and producing a pass gate control signal; a second control signal generator receiving the first control signal and the pass gate control signal and producing a plurality of second control signals; a third control signal generator receiving the pass gate control signal and producing a third control signal by combining the pass gate control signal and a delay signal of the pass gate control signal; and a fourth control signal generator receiving the first control signal, the plurality of second control signals and the third control signal and producing the pipelatch control signal.
摘要翻译：一种存储装置，其具有多个管线电路，其经由全局输入/输出线路存储来自存储器单元的数据;管线输入控制电路，用于响应于管线分配控制信号选择性地将管线电路耦合到全局输入/输出线;以及管计数信号发生器，用于控制所述管线电路和输出驱动器之间的数据路径，其中所述管道输送控制电路包括：第一控制信号发生器，接收第一控制信号和全局输入/输出线路信号并产生通过门控制信号; 接收第一控制信号和通过门控制信号并产生多个第二控制信号的第二控制信号发生器; 接收所述通过栅极控制信号并通过组合所述通过栅极控制信号和所述通过栅极控制信号的延迟信号而产生第三控制信号的第三控制信号发生器; 以及第四控制信号发生器，接收第一控制信号，多个第二控制信号和第三控制信号，并产生管线控制信号。

6. 发明授权

US5936899A Wafer burn-in test circuit of a semiconductor memory device 失效
标题翻译：半导体存储器件的晶片老化测试电路
公开(公告)号：US5936899A
公开(公告)日：1999-08-10
申请号：US964892
申请日：1997-11-05
申请人： Dong Sik Jeong
发明人： Dong Sik Jeong
IPC分类号： G01R31/26 , G11C29/34 , G11C7/00
CPC分类号： G11C29/34
摘要： A wafer burn-in test circuit of a semiconductor memory device which can provide a burn-in stress voltage by only using a prior word line driver without additional devices or circuits. The wafer burn-in test circuit of the present invention comprises a row address pre-decoding circuit for selecting and driving a predetermined word line by a combination composed of row address signals, a word line driving control circuit for outputting a first signal to selectively drive the word line when at least one signal among address signals pre-decoded by the row address pre-decoding circuit is enabled, and outputting a second signal to enable the all word lines with no relation to a logic status of the address signals when a wafer burn-in signal is inputted, and a row decoder circuit for receiving output signals provided from the row address pre-decoding circuit and the word line driving control circuit therein, and for selectively driving the word line by the address signal in a normal mode of operation and simultaneously driving a plurality of word lines in a wafer burn-in mode of operation.
摘要翻译：半导体存储器件的晶片老化测试电路，其可以通过仅使用现有的字线驱动器而不需要附加的器件或电路来提供老化的应力电压。本发明的晶片老化测试电路包括行地址预解码电路，用于通过由行地址信号组成的组合来选择和驱动预定字线;字线驱动控制电路，用于输出第一信号以选择性地驱动当由行地址预解码电路预解码的地址信号中的至少一个信号被使能时，字线被输出，并且当晶片处于不同时，输出第二信号以使得与所述地址信号的逻辑状态无关的所有字线输入老化信号，以及行解码器电路，用于接收从行地址预解码电路和字线驱动控制电路提供的输出信号，并且用于以正常模式的地址信号选择性地驱动字线在晶片老化模式下同时驱动多个字线。

7. 发明授权

US5926423A Wafer burn-in circuit for a semiconductor memory device 失效
标题翻译：用于半导体存储器件的晶片老化电路
公开(公告)号：US5926423A
公开(公告)日：1999-07-20
申请号：US964647
申请日：1997-11-05
申请人： Dong Sik Jeong
发明人： Dong Sik Jeong
IPC分类号： G01R31/26 , G11C29/02 , G11C29/50 , G11C7/00
CPC分类号： G11C29/025 , G11C29/02 , G11C29/50 , G11C11/401
摘要： A wafer burn-in circuit for a semiconductor memory device which can detect defected cells in an early stage and increase a yield by applying a stress to bit lines in a wafer state to detect the defected cells and repair the same according to the present invention, is disclosed. To this end, a wafer burn-in circuit for a semiconductor memory device according to the invention includes an equalizing means for bit line for equalizing said bit lines at a standby operation stage, wherein the equalizing means for bit line is controlled by a first precharge signal for bit line. A stress inputting means for bit line is provided to input a stress voltage to the bit lines at a wafer burn-in operation stage, wherein the stress inputting means for bit line is controlled by a second precharge signal for bit line. A stress transferring means for bit line is also provided to make its output to be in a floating state at an normal operation stage, whereas it outputs a stress voltage to the stress inputting means for bit lines at the wafer burn-in operation stage.
摘要翻译：一种用于半导体存储器件的晶片老化电路，其可以在早期阶段检测缺陷单元并且通过对晶片状态的位线施加应力来提高产量，以检测缺陷单元并根据本发明对其进行修复，被披露。为此，根据本发明的用于半导体存储器件的晶片老化电路包括用于在待机操作阶段对位线进行均衡的位线均衡装置，其中用于位线的均衡装置由第一预充电位线信号。提供了一种用于位线的应力输入装置，用于在晶片老化操作阶段向位线输入应力电压，其中用于位线的应力输入装置由用于位线的第二预充电信号控制。还提供了用于位线的应力传递装置以使其输出在正常操作阶段处于浮置状态，而在晶片老化操作阶段向位线的应力输入装置输出应力电压。

8. 发明授权

US5680359A Self-refresh period adjustment circuit for semiconductor memory device 失效
标题翻译：半导体存储器件的自刷新周期调整电路
公开(公告)号：US5680359A
公开(公告)日：1997-10-21
申请号：US619221
申请日：1996-03-21
申请人： Dong Sik Jeong
发明人： Dong Sik Jeong
IPC分类号： G11C11/406 , G11C11/402
CPC分类号： G11C11/40626 , G11C11/406 , G11C11/40615 , G11C2211/4068
摘要： A self-refresh period adjustment circuit for a semiconductor memory device. The self-refresh period adjustment circuit comprises a ring oscillator for generating a pulse signal with a fixed period for a self-refresh operation of the semiconductor memory device, a leakage current detector for detecting the amount of leakage current produced as charges stored in memory cells in the semiconductor memory device are discharged, and at least two temperature detectors for detecting a temperature variation of the semiconductor memory device, each of the at least two temperature detectors including a voltage divider and a comparator. The voltage divider divides a supply voltage and supplies the divided result as a reference signal to the comparator. The comparator compares an output signal from the leakage current detector with the reference signal from the voltage divider. The self-refresh period adjustment circuit further comprises at least two frequency dividers, each of the at least two frequency dividers dividing a frequency of an output signal from the ring oscillator at a desired ratio in response to an output signal from a corresponding one of the at least two temperature detectors to adjust a self-refresh period of the semiconductor memory device.
摘要翻译：一种用于半导体存储器件的自刷新周期调节电路。自刷新周期调整电路包括环形振荡器，用于产生用于半导体存储器件的自刷新操作的固定周期的脉冲信号;漏电流检测器，用于检测作为存储在存储单元中的电荷产生的漏电流量以及至少两个温度检测器，用于检测半导体存储器件的温度变化，所述至少两个温度检测器中的每一个包括分压器和比较器。分压器分压电源电压，并将分频结果作为参考信号提供给比较器。比较器将来自漏电流检测器的输出信号与分压器的参考信号进行比较。所述自刷新周期调整电路还包括至少两个分频器，所述至少两个分频器中的每一个响应于来自所述环路振荡器的相应的一个的输出信号以期望的比率将来自所述环形振荡器的输出信号的频率分频至少两个温度检测器，用于调整半导体存储器件的自刷新周期。

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