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1. 发明申请

US20120014201A1 DUAL RAIL MEMORY 有权
标题翻译：双轨记忆
公开(公告)号：US20120014201A1
公开(公告)日：2012-01-19
申请号：US12835197
申请日：2010-07-13
申请人： Derek C. TAO , Kuoyuan (Peter) HSU , Dong Sik JEONG , Young Suk KIM , Young Seog KIM , Yukit TANG
发明人： Derek C. TAO , Kuoyuan (Peter) HSU , Dong Sik JEONG , Young Suk KIM , Young Seog KIM , Yukit TANG
IPC分类号： G11C5/14
CPC分类号： G11C5/14
摘要： A memory comprising: a plurality of memory cells arranged in a plurality of rows and a plurality of columns. A column of the plurality of columns including a first power supply node configured to provide a first voltage, a second power supply node configured to provide a second voltage, a plurality of internal supply nodes electrically coupled together and configured to receive the first voltage or the second voltage for a plurality of memory cells in the column and a plurality of internal ground nodes. The internal ground nodes electrically coupled together and configured to provide at least two current paths for the plurality of memory cells in the column.
摘要翻译：一种存储器，包括：布置成多行和多列的多个存储单元。所述多列的列包括被配置为提供第一电压的第一电源节点，被配置为提供第二电压的第二电源节点，电耦合在一起并被配置为接收第一电压或该列中的多个存储单元的第二电压和多个内部接地节点。内部接地节点电耦合在一起并且被配置为为列中的多个存储器单元提供至少两个电流路径。

2. 发明申请

US20120008376A1 MEMORY WITH REGULATED GROUND NODES 有权
标题翻译：内存与管制地址
公开(公告)号：US20120008376A1
公开(公告)日：2012-01-12
申请号：US12832320
申请日：2010-07-08
申请人： Kuoyuan (Peter) HSU , Yukit TANG , Derek TAO , Young Seog KIM
发明人： Kuoyuan (Peter) HSU , Yukit TANG , Derek TAO , Young Seog KIM
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C11/419 , G11C7/00 , G11C11/413 , H01L27/11
摘要： Some embodiments regard a memory array comprising: a plurality of memory cells arranged in a plurality of rows and a plurality of columns; wherein a column of the plurality of columns includes a column ground node; at least two voltage sources configured to be selectively coupled to the column ground node; and a plurality of memory cells having a plurality of internal ground nodes electrically coupled together and to the column ground node.
摘要翻译：一些实施例涉及一种存储器阵列，包括：布置成多行和多列的多个存储单元; 其中所述多列的列包括列接地节点; 至少两个电压源被配置为选择性地耦合到所述列接地节点; 以及多个存储单元，其具有多个内部接地节点，所述多个内部接地节点电耦合在一起并连接到所述列接地节点。

3. 发明申请

US20130088925A1 LAYOUT OF MEMORY CELLS 有权
标题翻译：记忆细胞的布局
公开(公告)号：US20130088925A1
公开(公告)日：2013-04-11
申请号：US13267235
申请日：2011-10-06
申请人： Jacklyn CHANG , Derek C. TAO , Yukit TANG , Kuoyuan (Peter) HSU
发明人： Jacklyn CHANG , Derek C. TAO , Yukit TANG , Kuoyuan (Peter) HSU
IPC分类号： G11C7/10
CPC分类号： G11C7/18 , G11C11/412 , G11C11/413 , H01L27/0207 , H01L27/1104
摘要： A semiconductor structure includes a first strap cell, a first read port, and a first VSS terminal. The first strap cell has a first strap cell VSS region. The first read port has a first read port VSS region, a first read port read bit line region, and a first read port poly region. The first VSS terminal is configured to electrically couple the first strap cell VSS region and the first read port VSS region.
摘要翻译：半导体结构包括第一带状电池，第一读取端口和第一VSS端子。第一带状电池具有第一带电池VSS区域。第一读取端口具有第一读取端口VSS区域，第一读取端口读取位线区域和第一读取端口聚合区域。第一VSS端子被配置为电耦合第一带电池VSS区域和第一读取端口VSS区域。

4. 发明申请

US20130088926A1 TRACKING MECHANISMS 有权
标题翻译：跟踪机制
公开(公告)号：US20130088926A1
公开(公告)日：2013-04-11
申请号：US13253749
申请日：2011-10-05
申请人： Derek C. TAO , Annie-Li-Keow LUM , Yukit TANG , Kuoyuan (Peter) HSU
发明人： Derek C. TAO , Annie-Li-Keow LUM , Yukit TANG , Kuoyuan (Peter) HSU
IPC分类号： G11C7/10 , G11C7/00
CPC分类号： G11C7/222 , G11C7/10 , G11C7/1051 , G11C11/419
摘要： A tracking edge of a tracking signal is activated. A buffer is turned off and a latching circuit is turned on, based on the tracking edge of the tracking signal. A buffer output of the buffer is coupled to a latch output of the latching circuit at a node. The buffer receives a data line of a memory macro.
摘要翻译：跟踪信号的跟踪边缘被激活。基于跟踪信号的跟踪边缘，缓冲器被关闭并且锁存电路被接通。缓冲器的缓冲器输出耦合到节点处的锁存电路的锁存器输出。缓冲区接收一个内存宏的数据行。

5. 发明申请

US20110292753A1 MEMORY LEAKAGE AND DATA RETENTION CONTROL 有权
标题翻译：内存泄漏和数据保持控制
公开(公告)号：US20110292753A1
公开(公告)日：2011-12-01
申请号：US12788860
申请日：2010-05-27
申请人： Kuoyuan (Peter) HSU , Yukit TANG , Jacklyn CHANG
发明人： Kuoyuan (Peter) HSU , Yukit TANG , Jacklyn CHANG
IPC分类号： G11C5/14
CPC分类号： G11C5/148 , G11C11/413
摘要： A circuit with leakage and data retention control includes at least one memory cell in a first memory array. The at least one memory cell is coupled to a first power supply voltage and a virtual ground. The circuit includes a current source and an NMOS transistor. The drain of the NMOS transistor is coupled to the virtual ground and the gate of the NMOS transistor is coupled to the current source.
摘要翻译：具有泄漏和数据保持控制的电路包括第一存储器阵列中的至少一个存储单元。所述至少一个存储单元耦合到第一电源电压和虚拟地。该电路包括电流源和NMOS晶体管。 NMOS晶体管的漏极耦合到虚拟接地，并且NMOS晶体管的栅极耦合到电流源。

6. 发明申请

US20120051112A1 MEMORY DEVICES HAVING BREAK CELLS 有权
标题翻译：具有断裂细胞的记忆装置
公开(公告)号：US20120051112A1
公开(公告)日：2012-03-01
申请号：US12870925
申请日：2010-08-30
申请人： Yukit TANG , Kuoyuan HSU , Derek TAO
发明人： Yukit TANG , Kuoyuan HSU , Derek TAO
IPC分类号： G11C5/02
CPC分类号： G11C5/02 , G11C11/417
摘要： A representative memory device includes a cell array, at least one break cell that subdivides the cell array into bit cell arrays, and one or more power switches that are electrically coupled to the bit cell. In one embodiment, the break cell separates a connectivity of a first voltage and a second voltage between at least two bit cell arrays so that the bit cell arrays can be selectively coupled to either the first voltage or the second voltage using the power switches. The power switches control the connection of each separated bit cell array of the cell array to either the first voltage or second voltage.
摘要翻译：代表性的存储器件包括单元阵列，至少一个将单元阵列细分为位单元阵列的中断单元以及电耦合到位单元的一个或多个功率开关。在一个实施例中，中断单元在至少两个位单元阵列之间分离第一电压和第二电压的连通性，使得位单元阵列可以使用功率开关选择性地耦合到第一电压或第二电压。电源开关将单元阵列的每个分离的位单元阵列的连接控制为第一电压或第二电压。

7. 发明申请

US20120026805A1 SRAM BITCELL DATA RETENTION CONTROL FOR LEAKAGE OPTIMIZATION 有权
标题翻译： SRAM BITCELL数据保护控制用于泄漏优化
公开(公告)号：US20120026805A1
公开(公告)日：2012-02-02
申请号：US12846129
申请日：2010-07-29
申请人： Yukit TANG , Kuoyuan HSU
发明人： Yukit TANG , Kuoyuan HSU
IPC分类号： G11C7/00 , G11C5/14
CPC分类号： G11C11/412 , G11C5/147
摘要： An integrated circuit includes a static random access memory (SRAM) array coupled to a first voltage supply node and a second voltage supply node. The first and second voltage supply nodes provide a retention voltage across the SRAM array. A current limiter is disposed between the SRAM array and the first voltage supply node, and a voltage regulator is coupled in parallel with the current limiter between the SRAM array and the first voltage supply node. The voltage regulator is configured to maintain the retention voltage across the SRAM array above a predetermined level.
摘要翻译：集成电路包括耦合到第一电压供应节点和第二电压供应节点的静态随机存取存储器（SRAM）阵列。第一和第二电压供应节点提供跨SRAM阵列的保持电压。限流器设置在SRAM阵列和第一电压供应节点之间，并且电压调节器与SRAM阵列和第一电压供应节点之间的限流器并联耦合。电压调节器被配置为将SRAM阵列上的保持电压保持在预定水平以上。

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