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1. 发明申请

US20050054171A1 Incorporation of carbon in silicon/silicon germanium epitaxial layer to enhance yield for Si-Ge bipolar technology 有权
标题翻译：在硅/硅锗外延层中引入碳以提高Si-Ge双极技术的产量
公开(公告)号：US20050054171A1
公开(公告)日：2005-03-10
申请号：US10953378
申请日：2004-09-29
申请人： Jack Chu , Douglas Coolbaugh , James Dunn , David Greenberg , David Harame , Basanth Jagannathan , Robb Johnson , Louis Lanzerotti , Kathryn Schonenberg , Ryan Wuthrich
发明人： Jack Chu , Douglas Coolbaugh , James Dunn , David Greenberg , David Harame , Basanth Jagannathan , Robb Johnson , Louis Lanzerotti , Kathryn Schonenberg , Ryan Wuthrich
IPC分类号： H01L21/331 , H01L29/737 , H01L21/8222
CPC分类号： H01L29/66242 , H01L21/02381 , H01L21/02447 , H01L21/02529 , H01L21/02532 , H01L21/02579 , H01L21/0262 , H01L29/1004 , H01L29/161 , H01L29/7378
摘要： A SiGe bipolar transistor containing substantially no dislocation defects present between the emitter and collector region and a method of forming the same are provided. The SiGe bipolar transistor includes a collector region of a first conductivity type; a SiGe base region formed on a portion of said collector region; and an emitter region of said first conductivity type formed over a portion of said base region, wherein said collector region and said base region include carbon continuously therein. The SiGe base region is further doped with boron.
摘要翻译：提供了在发射极和集电极区域之间基本上不存在位错缺陷的SiGe双极晶体管及其形成方法。 SiGe双极晶体管包括第一导电类型的集电极区域; 形成在所述集电区域的一部分上的SiGe基区; 以及形成在所述基极区域的一部分上的所述第一导电类型的发射极区域，其中所述集电极区域和所述基极区域在其中连续地包括碳。 SiGe基区进一步掺硼。

2. 发明申请

US20060270203A1 VARIED IMPURITY PROFILE REGION FORMATION FOR VARYING BREAKDOWN VOLTAGE OF DEVICES 失效
标题翻译：变化的设备的破坏电压的变化区域形成
公开(公告)号：US20060270203A1
公开(公告)日：2006-11-30
申请号：US10908884
申请日：2005-05-31
申请人： Douglas Coolbaugh , Louis Lanzerotti , Bradley Orner , Jay Rascoe , David Sheridan , Stephen St. Onge
发明人： Douglas Coolbaugh , Louis Lanzerotti , Bradley Orner , Jay Rascoe , David Sheridan , Stephen St. Onge
IPC分类号： H01L21/425
CPC分类号： H01L21/8222 , H01L21/266 , H01L27/0825 , H01L29/0821 , H01L29/36
摘要： Methods are disclosed for forming a varied impurity profile for a collector using scattered ions while simultaneously forming a subcollector. In one embodiment, the invention includes: providing a substrate; forming a mask layer on the substrate including a first opening having a first dimension; and substantially simultaneously forming through the first opening a first impurity region at a first depth in the substrate (subcollector) and a second impurity region at a second depth different than the first depth in the substrate. The breakdown voltage of a device can be controlled by the size of the first dimension, i.e., the distance of first opening to an active region of the device. Numerous different sized openings can be used to provide devices with different breakdown voltages using a single mask and single implant. A semiconductor device is also disclosed.
摘要翻译：公开了用于使用散射离子形成收集器的不同杂质分布的同时形成子集电极的方法。在一个实施例中，本发明包括：提供衬底; 在所述基板上形成掩模层，所述掩模层包括具有第一尺寸的第一开口; 并且基本上同时地通过第一开口形成在衬底（子集电极）中的第一深度处的第一杂质区域和与衬底中的第一深度不同的第二深度的第二杂质区域。装置的击穿电压可以通过第一尺寸的尺寸，即第一开口到装置的有源区域的距离来控制。可以使用许多不同尺寸的开口来使用单个掩模和单个植入物来提供具有不同击穿电压的装置。还公开了一种半导体器件。

3. 发明申请

US20070275534A1 VARIED IMPURITY PROFILE REGION FORMATION FOR VARYING BREAKDOWN VOLTAGE OF DEVICES 有权
标题翻译：变化的设备的破坏电压的变化区域形成
公开(公告)号：US20070275534A1
公开(公告)日：2007-11-29
申请号：US11839106
申请日：2007-08-15
申请人： Douglas Coolbaugh , Louis Lanzerotti , Bradley Orner , Jay Rascoe , David Sheridan , Stephen St. Onge
发明人： Douglas Coolbaugh , Louis Lanzerotti , Bradley Orner , Jay Rascoe , David Sheridan , Stephen St. Onge
IPC分类号： H01L21/331
CPC分类号： H01L21/8222 , H01L21/266 , H01L27/0825 , H01L29/0821 , H01L29/36
摘要： Methods are disclosed for forming a varied impurity profile for a collector using scattered ions while simultaneously forming a subcollector. In one embodiment, the invention includes: providing a substrate; forming a mask layer on the substrate including a first opening having a first dimension; and substantially simultaneously forming through the first opening a first impurity region at a first depth in the substrate (subcollector) and a second impurity region at a second depth different than the first depth in the substrate. The breakdown voltage of a device can be controlled by the size of the first dimension, i.e., the distance of first opening to an active region of the device. Numerous different sized openings can be used to provide devices with different breakdown voltages using a single mask and single implant. A semiconductor device is also disclosed.
摘要翻译：公开了用于使用散射离子形成收集器的不同杂质分布的同时形成子集电极的方法。在一个实施例中，本发明包括：提供衬底; 在所述基板上形成掩模层，所述掩模层包括具有第一尺寸的第一开口; 并且基本上同时地通过第一开口形成在衬底（子集电极）中的第一深度处的第一杂质区域和与衬底中的第一深度不同的第二深度的第二杂质区域。装置的击穿电压可以通过第一尺寸的尺寸，即第一开口到装置的有源区域的距离来控制。可以使用许多不同尺寸的开口来使用单个掩模和单个植入物来提供具有不同击穿电压的装置。还公开了一种半导体器件。

4. 发明申请

US20070096257A1 SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURE 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US20070096257A1
公开(公告)日：2007-05-03
申请号：US11163882
申请日：2005-11-02
申请人： Douglas Coolbaugh , Alvin Joseph , Seong-dong Kim , Louis Lanzerotti , Xuefeng Liu , Robert Rassel
发明人： Douglas Coolbaugh , Alvin Joseph , Seong-dong Kim , Louis Lanzerotti , Xuefeng Liu , Robert Rassel
IPC分类号： H01L27/102
CPC分类号： H01L27/0814 , H01L27/0664 , H01L27/0823 , H01L29/0821 , H01L29/7371 , H01L29/868
摘要： A structure comprises a single wafer with a first subcollector formed in a first region having a first thickness and a second subcollector formed in a second region having a second thickness, different from the first thickness. A method is also contemplated which includes providing a substrate including a first layer and forming a first doped region in the first layer. The method further includes forming a second layer on the first layer and forming a second doped region in the second layer. The second doped region is formed at a different depth than the first doped region. The method also includes forming a first reachthrough in the first layer and forming a second reachthrough in second layer to link the first reachthrough to the surface.
摘要翻译：一种结构包括具有形成在具有第一厚度的第一区域中的第一子集电极的单晶片和形成在具有不同于第一厚度的第二厚度的第二区域中的第二子集电极。还可以设想一种方法，其包括提供包括第一层并在第一层中形成第一掺杂区的衬底。该方法还包括在第一层上形成第二层并在第二层中形成第二掺杂区域。第二掺杂区形成在与第一掺杂区不同的深度。该方法还包括在第一层中形成第一通道并在第二层中形成第二通道以将第一通道连接到表面。

5. 发明申请

US20080099787A1 SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURE 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US20080099787A1
公开(公告)日：2008-05-01
申请号：US11873696
申请日：2007-10-17
申请人： Douglas Coolbaugh , Alvin Joseph , Seong-dong Kim , Louis Lanzerotti , Xuefeng Liu , Robert Rassel
发明人： Douglas Coolbaugh , Alvin Joseph , Seong-dong Kim , Louis Lanzerotti , Xuefeng Liu , Robert Rassel
IPC分类号： H01L27/06
CPC分类号： H01L27/0814 , H01L27/0664 , H01L27/0823 , H01L29/0821 , H01L29/7371 , H01L29/868
摘要： A structure comprises a single wafer with a first subcollector formed in a first region having a first thickness and a second subcollector formed in a second region having a second thickness, different from the first thickness. A method is also contemplated which includes providing a substrate including a first layer and forming a first doped region in the first layer. The method further includes forming a second layer on the first layer and forming a second doped region in the second layer. The second doped region is formed at a different depth than the first doped region. The method also includes forming a first reachthrough in the first layer and forming a second reachthrough in second layer to link the first reachthrough to the surface.
摘要翻译：一种结构包括具有形成在具有第一厚度的第一区域中的第一子集电极的单晶片和形成在具有不同于第一厚度的第二厚度的第二区域中的第二子集电极。还可以设想一种方法，其包括提供包括第一层并在第一层中形成第一掺杂区的衬底。该方法还包括在第一层上形成第二层并在第二层中形成第二掺杂区域。第二掺杂区形成在与第一掺杂区不同的深度。该方法还包括在第一层中形成第一通道并在第二层中形成第二通道以将第一通道连接到表面。

6. 发明申请

US20050245038A1 Novel varactors for CMOS and BiCMOS technologies 失效
标题翻译：用于CMOS和BiCMOS技术的新型变容二极管
公开(公告)号：US20050245038A1
公开(公告)日：2005-11-03
申请号：US11053721
申请日：2005-02-08
申请人： Douglas Coolbaugh , James Dunn , Michael Gordon , Mohamed Hammad , Jeffrey Johnson , David Sheridan
发明人： Douglas Coolbaugh , James Dunn , Michael Gordon , Mohamed Hammad , Jeffrey Johnson , David Sheridan
IPC分类号： H01L21/8222 , H01L27/08 , H01L29/93 , H01L29/94
CPC分类号： H01L27/0811 , H01L27/0808 , H01L29/93 , H01L29/94
摘要： Varactors are provided which have a high tunability and/or a high quality factor associated therewith as well as methods for fabricating the same. One type of varactor disclosed is a quasi hyper-abrupt base-collector junction varactor which includes a substrate having a collector region of a first conductivity type atop a subcollector region, the collector region having a plurality of isolation regions present therein; reach-through implant regions located between at least a pair of the isolation regions; a SiGe layer atop a portion of the substrate not containing a reach-through implant region, the SiGe layer having an extrinsic base region of a second conductivity type which is different from the first conductivity type; and an antimony implant region located between the extrinsic base region and the subcollector region. Another type of varactor disclosed is an MOS varactor which includes at least a poly gate region and a well region wherein the poly gate region and the well region have opposite polarities.
摘要翻译：提供了具有高可调性和/或与之相关的高品质因素的变形反应器及其制造方法。公开的一种类型的变容二极管是准超突发的基极 - 集电极结变容二极管，其包括在子集电极区域顶部具有第一导电类型的集电极区域的基板，所述集电极区域中存在多个隔离区域; 位于至少一对隔离区之间的贯穿植入区; 所述SiGe层位于所述衬底的不包含直通注入区域的部分之上，所述SiGe层具有不同于所述第一导电类型的第二导电类型的非本征基区; 以及位于外部基极区域和子集电极区域之间的锑注入区域。所公开的另一种类型的变容二极管是MOS变容二极管，其至少包括多晶硅栅极区域和阱区域，其中多晶硅栅极区域和阱区域具有相反的极性。

7. 发明申请

US20070290272A1 INTEGRATED THIN-FILM RESISTOR WITH DIRECT CONTACT 有权
标题翻译：集成薄膜电阻与直接接触
公开(公告)号：US20070290272A1
公开(公告)日：2007-12-20
申请号：US11846595
申请日：2007-08-29
申请人： Eric Coker , Douglas Coolbaugh , Ebenezer Eshun , Zhong-Xiang He , Matthew Moon , Anthony Stamper
发明人： Eric Coker , Douglas Coolbaugh , Ebenezer Eshun , Zhong-Xiang He , Matthew Moon , Anthony Stamper
IPC分类号： H01L29/00
CPC分类号： H01L27/016
摘要： A BEOL thin-film resistor adapted for flexible integration rests on a first layer of ILD. The thickness of the first layer of ILD and the resistor thickness combine to match the nominal design thickness of vias in the layer of concern. A second layer of ILD matches the resistor thickness and is planarized to the top surface of the resistor. A third layer of ILD has a thickness equal to the nominal value of the interconnections on this layer. Dual damascene interconnection apertures and apertures for making contact with the resistor are formed simultaneously, with the etch stop upper cap layer in the resistor protecting the resistive layer while the vias in the dual damascene apertures are formed.
摘要翻译：适用于灵活集成的BEOL薄膜电阻依赖于第一层ILD。 ILD的第一层的厚度和电阻器厚度相结合，以匹配所涉及的层中的通孔的标称设计厚度。第二层ILD匹配电阻器厚度，并平坦化到电阻器的顶表面。 ILD的第三层具有等于该层上互连的标称值的厚度。同时形成用于与电阻器接触的双镶嵌互连孔和孔，电阻器中的蚀刻停止上盖层保护电阻层，同时形成双镶嵌孔中的通孔。

8. 发明申请

US20070190760A1 INTEGRATED PARALLEL PLATE CAPACITORS 有权
标题翻译：集成并联板电容器
公开(公告)号：US20070190760A1
公开(公告)日：2007-08-16
申请号：US11275544
申请日：2006-01-13
申请人： Douglas Coolbaugh , Hanyi Ding , Ebenezer Eshun , Michael Gordon , Zhong-Xiang He , Anthony Stamper
发明人： Douglas Coolbaugh , Hanyi Ding , Ebenezer Eshun , Michael Gordon , Zhong-Xiang He , Anthony Stamper
IPC分类号： H01L21/425
CPC分类号： H01L23/5223 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： A parallel plate capacitor formed in the back end of an integrated circuit employs conductive capacitor plates that are formed simultaneously with the other interconnects on that level of the back end (having the same material, thickness, etc). The capacitor plates are set into the interlevel dielectric using the same process as the other interconnects on that level of the back end (preferably dual damascene). Some versions of the capacitors have perforations in the plates and vertical conductive members connecting all plates of the same polarity, thereby increasing reliability, saving space and increasing the capacitive density compared with solid plates.
摘要翻译：形成在集成电路的后端的平行电容器采用与后端（具有相同材料，厚度等）的该级别上的其它互连件同时形成的导电电容器板。使用与后端（优选双镶嵌）级别上的其它互连件相同的工艺将电容器板设置在层间电介质中。一些版本的电容器在板中具有穿孔，并且垂直导电构件连接相同极性的所有板，从而与实心板相比增加了可靠性，节省了空间并增加了电容密度。

9. 发明申请

US20070152332A1 SINGLE OR DUAL DAMASCENE VIA LEVEL WIRINGS AND/OR DEVICES, AND METHODS OF FABRICATING SAME 审中-公开
标题翻译：通过水平线和/或器件的单或双倍增益，以及制造方法
公开(公告)号：US20070152332A1
公开(公告)日：2007-07-05
申请号：US11306596
申请日：2006-01-04
申请人： Anil Chinthakindi , Douglas Coolbaugh , Ebenezer Eshun , Vincent McGahay , Anthony Stamper , Kunal Vaed , Richard Volant
发明人： Anil Chinthakindi , Douglas Coolbaugh , Ebenezer Eshun , Vincent McGahay , Anthony Stamper , Kunal Vaed , Richard Volant
IPC分类号： H01L21/44
CPC分类号： H01L21/76838 , H01L23/5223 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要： The present invention relates to integrated circuits that comprise via-level wirings and/or devices. Specifically, an integrate circuit of the present invention comprises a first line level and a second line level spaced apart from each other, with a via level therebetween. The first and second line levels both comprise metal wirings and/or electronic devices. The via level comprises at least one metal via that extends therethrough to electrically connect the first line level with the second line level. Further, the via level comprises at least one via-level metal wiring and/or electronic device.
摘要翻译：本发明涉及包括通孔级布线和/或器件的集成电路。具体而言，本发明的集成电路包括彼此间隔开的第一线路电平和第二线路电平，其间具有通路电平。第一和第二线路级均包括金属布线和/或电子设备。通孔级包括至少一个穿过其中的金属通孔，以将第一线路电平与第二线路电平电连接。此外，通孔电平包括至少一个通孔级金属布线和/或电子器件。

10. 发明申请

US20070105354A1 BURIED SUBCOLLECTOR FOR HIGH FREQUENCY PASSIVE DEVICES 失效
标题翻译：用于高频无源器件的BURIED SUBCOLLECTOR
公开(公告)号：US20070105354A1
公开(公告)日：2007-05-10
申请号：US11164108
申请日：2005-11-10
申请人： Douglas Coolbaugh , Xuefeng Liu , Robert Rassel , David Sheridan
发明人： Douglas Coolbaugh , Xuefeng Liu , Robert Rassel , David Sheridan
IPC分类号： H01L21/425
CPC分类号： H01L21/8249 , H01L29/0821 , H01L29/66272
摘要： A method of fabricating a buried subcollector in which the buried subcollector is implanted to a depth in which during subsequent epi growth the buried subcollector remains substantially below the fictitious interface between the epi layer and the substrate is provided. In particular, the inventive method forms a buried subcollector having an upper surface (i.e., junction) that is located at a depth from about 3000 Å or greater from the upper surface of the semiconductor substrate. This deep buried subcollector having an upper surface that is located at a depth from about 3000 Å or greater from the upper surface of the substrate is formed using a reduced implant energy (as compared to a standard deep implanted subcollector process) at a relative high dose. The present invention also provides a semiconductor structure including the inventive buried subcollector which can be used as cathode for passive devices in high frequency applications.
摘要翻译：一种制造掩埋子集电极的方法，其中将埋入的子集电极注入深度，其中在随后的外延生长期间，掩埋子集电极基本上保持在外延层和衬底之间的虚拟界面的下方。特别地，本发明的方法形成了具有从半导体衬底的上表面位于距离大约或更大的深度的上表面（即结）的掩埋子集电极。该深埋底部集电器具有从衬底的上表面位于距离大约等于或更大的深度的上表面，其使用相对高剂量的减少的注入能量（与标准深度植入子集电极过程相比）。本发明还提供了一种半导体结构，其包括本发明的掩埋子集电极，其可以用作高频应用中的无源器件的阴极。

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