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1. 发明申请

US20070096257A1 SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURE 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US20070096257A1
公开(公告)日：2007-05-03
申请号：US11163882
申请日：2005-11-02
申请人： Douglas Coolbaugh , Alvin Joseph , Seong-dong Kim , Louis Lanzerotti , Xuefeng Liu , Robert Rassel
发明人： Douglas Coolbaugh , Alvin Joseph , Seong-dong Kim , Louis Lanzerotti , Xuefeng Liu , Robert Rassel
IPC分类号： H01L27/102
CPC分类号： H01L27/0814 , H01L27/0664 , H01L27/0823 , H01L29/0821 , H01L29/7371 , H01L29/868
摘要： A structure comprises a single wafer with a first subcollector formed in a first region having a first thickness and a second subcollector formed in a second region having a second thickness, different from the first thickness. A method is also contemplated which includes providing a substrate including a first layer and forming a first doped region in the first layer. The method further includes forming a second layer on the first layer and forming a second doped region in the second layer. The second doped region is formed at a different depth than the first doped region. The method also includes forming a first reachthrough in the first layer and forming a second reachthrough in second layer to link the first reachthrough to the surface.
摘要翻译：一种结构包括具有形成在具有第一厚度的第一区域中的第一子集电极的单晶片和形成在具有不同于第一厚度的第二厚度的第二区域中的第二子集电极。还可以设想一种方法，其包括提供包括第一层并在第一层中形成第一掺杂区的衬底。该方法还包括在第一层上形成第二层并在第二层中形成第二掺杂区域。第二掺杂区形成在与第一掺杂区不同的深度。该方法还包括在第一层中形成第一通道并在第二层中形成第二通道以将第一通道连接到表面。

2. 发明申请

US20080099787A1 SEMICONDUCTOR STRUCTURE AND METHOD OF MANUFACTURE 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US20080099787A1
公开(公告)日：2008-05-01
申请号：US11873696
申请日：2007-10-17
申请人： Douglas Coolbaugh , Alvin Joseph , Seong-dong Kim , Louis Lanzerotti , Xuefeng Liu , Robert Rassel
发明人： Douglas Coolbaugh , Alvin Joseph , Seong-dong Kim , Louis Lanzerotti , Xuefeng Liu , Robert Rassel
IPC分类号： H01L27/06
CPC分类号： H01L27/0814 , H01L27/0664 , H01L27/0823 , H01L29/0821 , H01L29/7371 , H01L29/868
摘要： A structure comprises a single wafer with a first subcollector formed in a first region having a first thickness and a second subcollector formed in a second region having a second thickness, different from the first thickness. A method is also contemplated which includes providing a substrate including a first layer and forming a first doped region in the first layer. The method further includes forming a second layer on the first layer and forming a second doped region in the second layer. The second doped region is formed at a different depth than the first doped region. The method also includes forming a first reachthrough in the first layer and forming a second reachthrough in second layer to link the first reachthrough to the surface.
摘要翻译：一种结构包括具有形成在具有第一厚度的第一区域中的第一子集电极的单晶片和形成在具有不同于第一厚度的第二厚度的第二区域中的第二子集电极。还可以设想一种方法，其包括提供包括第一层并在第一层中形成第一掺杂区的衬底。该方法还包括在第一层上形成第二层并在第二层中形成第二掺杂区域。第二掺杂区形成在与第一掺杂区不同的深度。该方法还包括在第一层中形成第一通道并在第二层中形成第二通道以将第一通道连接到表面。

3. 发明申请

US20070105354A1 BURIED SUBCOLLECTOR FOR HIGH FREQUENCY PASSIVE DEVICES 失效
标题翻译：用于高频无源器件的BURIED SUBCOLLECTOR
公开(公告)号：US20070105354A1
公开(公告)日：2007-05-10
申请号：US11164108
申请日：2005-11-10
申请人： Douglas Coolbaugh , Xuefeng Liu , Robert Rassel , David Sheridan
发明人： Douglas Coolbaugh , Xuefeng Liu , Robert Rassel , David Sheridan
IPC分类号： H01L21/425
CPC分类号： H01L21/8249 , H01L29/0821 , H01L29/66272
摘要： A method of fabricating a buried subcollector in which the buried subcollector is implanted to a depth in which during subsequent epi growth the buried subcollector remains substantially below the fictitious interface between the epi layer and the substrate is provided. In particular, the inventive method forms a buried subcollector having an upper surface (i.e., junction) that is located at a depth from about 3000 Å or greater from the upper surface of the semiconductor substrate. This deep buried subcollector having an upper surface that is located at a depth from about 3000 Å or greater from the upper surface of the substrate is formed using a reduced implant energy (as compared to a standard deep implanted subcollector process) at a relative high dose. The present invention also provides a semiconductor structure including the inventive buried subcollector which can be used as cathode for passive devices in high frequency applications.
摘要翻译：一种制造掩埋子集电极的方法，其中将埋入的子集电极注入深度，其中在随后的外延生长期间，掩埋子集电极基本上保持在外延层和衬底之间的虚拟界面的下方。特别地，本发明的方法形成了具有从半导体衬底的上表面位于距离大约或更大的深度的上表面（即结）的掩埋子集电极。该深埋底部集电器具有从衬底的上表面位于距离大约等于或更大的深度的上表面，其使用相对高剂量的减少的注入能量（与标准深度植入子集电极过程相比）。本发明还提供了一种半导体结构，其包括本发明的掩埋子集电极，其可以用作高频应用中的无源器件的阴极。

4. 发明申请

US20080067623A1 LATERAL SILICIDED DIODES 有权
标题翻译：横向硅胶二极管
公开(公告)号：US20080067623A1
公开(公告)日：2008-03-20
申请号：US11944839
申请日：2007-11-26
申请人： Douglas Coolbaugh , Jeffrey Johnson , Xuefeng Liu , Bradley Orner , Robert Rassel , David Sheridan
发明人： Douglas Coolbaugh , Jeffrey Johnson , Xuefeng Liu , Bradley Orner , Robert Rassel , David Sheridan
IPC分类号： H01L29/872
CPC分类号： H01L29/872 , H01L29/0657 , H01L29/417 , H01L29/66136 , H01L29/66143 , H01L29/861 , H01L29/868
摘要： A structure and method of fabricating lateral diodes. The diodes include Schottky diodes and PIN diodes. The method of fabrication includes forming one or more doped regions and more trenches in a silicon substrate and forming metal silicides on the sidewalls of the trenches. The fabrication of lateral diodes may be integrated with the fabrication of field effect, bipolar and SiGe bipolar transistors.
摘要翻译：制造横向二极管的结构和方法。二极管包括肖特基二极管和PIN二极管。制造方法包括在硅衬底中形成一个或多个掺杂区域和更多沟槽，并在沟槽的侧壁上形成金属硅化物。横向二极管的制造可以与场效应，双极和SiGe双极晶体管的制造集成。

5. 发明申请

US20060071292A1 REDUCED GUARD RING IN SCHOTTKY BARRIER DIODE STRUCTURE 失效
标题翻译：肖特基二极管结构中的降低保护环
公开(公告)号：US20060071292A1
公开(公告)日：2006-04-06
申请号：US10711744
申请日：2004-10-01
申请人： Douglas Coolbaugh , Ebenezer Eshun , Alvin Joseph , Robert Rassel
发明人： Douglas Coolbaugh , Ebenezer Eshun , Alvin Joseph , Robert Rassel
IPC分类号： H01L29/93 , H01L31/108
CPC分类号： H01L29/66143 , H01L29/0615 , H01L29/0692 , H01L29/872
摘要： Schottky barrier diodes use a dielectric separation region to bound an active region. The dielectric separation region permits the elimination of a guard ring in at least one dimension. Further, using a dielectric separation region in an active portion of the integrated circuit device may reduce or eliminate parasitic capacitance by eliminating this guard ring.
摘要翻译：肖特基势垒二极管使用介电分离区域结合活性区域。电介质分离区允许在至少一个维度上消除保护环。此外，在集成电路器件的有源部分中使用介质分离区可以通过消除该保护环来减少或消除寄生电容。

6. 发明申请

US20070029587A1 MOS VARACTOR WITH SEGMENTED GATE DOPING 失效
标题翻译：具有隔离门的MOS变送器
公开(公告)号：US20070029587A1
公开(公告)日：2007-02-08
申请号：US11161533
申请日：2005-08-08
申请人： Heidi Greer , Seong-Dong Kim , Robert Rassel , Kunal Vaed
发明人： Heidi Greer , Seong-Dong Kim , Robert Rassel , Kunal Vaed
IPC分类号： H01L29/76 , H01L21/8234
CPC分类号： H01L29/93 , H01L27/0811 , H01L29/36 , H01L29/94
摘要： A MOS varactor is formed having a gate electrode comprising at least two abutting oppositely doped regions shorted together, in which the two regions are implanted simultaneously with source/drain implants for first and second types of transistor; at least one contact to a lower electrode is also formed simultaneously with the source/drain implants for the first type of transistor; the varactor insulator is formed simultaneously with the gate insulator for one type of transistor; and the lower electrode is formed simultaneously with a well for the first type of transistor, so that no additional mask is required.
摘要翻译：形成MOS变容二极管，其栅极电极包括至少两个彼此短接的邻接的相对掺杂区域，其中两个区域与用于第一和第二类型晶体管的源极/漏极注入同时注入; 与第一类型的晶体管的源极/漏极注入同时形成与下部电极的至少一个接触; 变容二极管与栅绝缘体同时形成一种晶体管; 并且下电极与用于第一类型晶体管的阱同时形成，使得不需要附加掩模。

7. 发明申请

US20070099386A1 INTEGRATION SCHEME FOR HIGH GAIN FET IN STANDARD CMOS PROCESS 审中-公开
标题翻译：标准CMOS工艺中高增益FET的集成方案
公开(公告)号：US20070099386A1
公开(公告)日：2007-05-03
申请号：US11163791
申请日：2005-10-31
申请人： Douglas Coolbaugh , Ebenezer Eshun , Robert Rassel , James Slinkman , Michael Zierak
发明人： Douglas Coolbaugh , Ebenezer Eshun , Robert Rassel , James Slinkman , Michael Zierak
IPC分类号： H01L21/336 , H01L29/788
CPC分类号： H01L29/66659 , H01L21/26586
摘要： A method for fabricating high gain FETs that substantially reduces or eliminates unwanted variation in device characteristics caused by using a prior art shadow masking process is provided. The inventive method employs a blocking mask that at least partially extends over the gate region wherein after extension and halo implants an FET having an asymmetric halo region asymmetric extension regions or a combination thereof is fabricated. The inventive method thus provides high gain FETs in which the variation of device characteristics is substantially reduced. The present invention also relates to the resulting asymmetric high gain FET device that is fabricated utilizing the method of the present invention.
摘要翻译：提供了一种制造高增益FET的方法，其基本上减少或消除了由使用现有技术的阴影掩蔽处理引起的器件特性的不必要的变化。本发明的方法采用阻挡掩模，其在栅极区域上至少部分地延伸，其中在延伸和卤素注入之后，制造具有不对称卤素区域不对称延伸区域或其组合的FET。因此，本发明的方法提供了高增益FET，其中器件特性的变化显着降低。本发明还涉及利用本发明的方法制造的非对称高增益FET器件。

8. 发明申请

US20060145300A1 METHOD FOR FORMING A ONE MASK HYPERABRUPT JUNCTION VARACTOR USING A COMPENSATED CATHODE CONTACT 有权
标题翻译：使用补偿阴极接触形成一个掩模超高压连接器的方法
公开(公告)号：US20060145300A1
公开(公告)日：2006-07-06
申请号：US10905486
申请日：2005-01-06
申请人： Douglas Coolbaugh , Stephen Furkay , Jeffrey Johnson , Robert Rassel
发明人： Douglas Coolbaugh , Stephen Furkay , Jeffrey Johnson , Robert Rassel
IPC分类号： H01L29/93 , H01L21/20
CPC分类号： H01L29/93
摘要： A semiconductor structure comprising a hyperabrupt junction varactor with a compensated cathode contact as well as a method of fabricating the same are disclosed. The method includes a single implant mask which is used in forming the subcollector/cathode, collector/well and hyperabrupt junction.
摘要翻译：公开了一种半导体结构，其包括具有补偿的阴极接触的超级连接变容二极管及其制造方法。该方法包括用于形成子集电极/阴极，集电极/阱和超破裂结的单个注入掩模。

9. 发明申请

US20060145296A1 TUNABLE TEMPERATURE COEFFICIENT OF RESISTANCE RESISTORS AND METHOD OF FABRICATING SAME 有权
标题翻译：电阻电阻的温度系数及其制造方法
公开(公告)号：US20060145296A1
公开(公告)日：2006-07-06
申请号：US10905473
申请日：2005-01-06
申请人： Douglas Coolbaugh , Ebenezer Eshun , Richard Rassel , Robert Rassel
发明人： Douglas Coolbaugh , Ebenezer Eshun , Richard Rassel , Robert Rassel
IPC分类号： H01L29/00
CPC分类号： H01L28/20
摘要： Tunable TCR resistors incorporated into integrated circuits and a method fabricating the tunable TCR resistors. The tunable TCR resistors including two or more resistors of two or more different materials having opposite polarity and different magnitude TCRs, the same polarity and different magnitude TCRs or having opposite polarity and about the same TCRs.
摘要翻译：整合在集成电路中的可调TCR电阻和制造可调TCR电阻的方法。可调TCR电阻器包括具有相反极性和不同幅度TCR，相同极性和不同幅度TCR或具有相反极性和大约相同TCR的两种或更多种不同材料的两个或更多个电阻器。

10. 发明申请

US20060043454A1 MOS VARACTOR USING ISOLATION WELL 有权
标题翻译：使用隔离的MOS变压器
公开(公告)号：US20060043454A1
公开(公告)日：2006-03-02
申请号：US10711144
申请日：2004-08-27
申请人： Douglas Coolbaugh , Douglas Hershberger , Robert Rassel
发明人： Douglas Coolbaugh , Douglas Hershberger , Robert Rassel
IPC分类号： H01L29/94 , H01L21/20
CPC分类号： H01L29/93 , H01L29/94
摘要： The present invention provides a varactor that has increased tunability and a high quality factor Q as well as a method of fabricating the varactor. The method of the present invention can be integrated into a conventional CMOS processing scheme or into a conventional BiCMOS processing scheme. The method includes providing a structure that includes a semiconductor substrate of a first conductivity type and optionally a subcollector or isolation well (i.e., doped region) of a second conductivity type located below an upper region of the substrate, the first conductivity type is different from said second conductivity type. Next, a plurality of isolation regions are formed in the upper region of the substrate and then a well region is formed in the upper region of the substrate. In some cases, the doped region is formed at this point of the inventive process. The well region includes outer well regions of the second conductivity type and an inner well region of the first conductivity type. Each well of said well region is separated at an upper surface by an isolation region. A field effect transistor having at least a gate conductor of the first conductivity type is then formed above the inner well region.
摘要翻译：本发明提供一种具有增加的可调性和高品质因数Q的变容二极管以及制造变容二极管的方法。本发明的方法可以集成到常规的CMOS处理方案中，或者被整合到常规的BiCMOS处理方案中。该方法包括提供包括第一导电类型的半导体衬底和位于衬底的上部区域下方的第二导电类型的子集电极或隔离阱（即，掺杂区）的结构，第一导电类型不同于所述第二导电类型。接下来，在基板的上部区域形成多个隔离区域，然后在基板的上部区域形成阱区域。在一些情况下，在本发明方法的这一点形成掺杂区域。阱区包括第二导电类型的外阱区和第一导电类型的内阱区。所述阱区的每个阱在上表面被隔离区分开。然后形成至少具有第一导电类型的栅极导体的场效应晶体管，并在内部阱区域的上方形成。

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