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1. 发明申请

US20050048735A1 BIPOLAR TRANSISTOR HAVING RAISED EXTRINSIC BASE WITH SELECTABLE SELF-ALIGNMENT AND METHODS OF FORMING SAME 有权
标题翻译：具有可选择的自对准的提升的超级基座的双极晶体管及其形成方法
公开(公告)号：US20050048735A1
公开(公告)日：2005-03-03
申请号：US10604988
申请日：2003-08-29
申请人： Marwan Khater , James Dunn , David Harame , Alvin Joseph , Qizhi Liu , Francois Pagette , Stephen St. Onge , Andreas Stricker
发明人： Marwan Khater , James Dunn , David Harame , Alvin Joseph , Qizhi Liu , Francois Pagette , Stephen St. Onge , Andreas Stricker
IPC分类号： H01L21/331 , H01L29/10 , H01L29/732 , H01L29/737 , H01L21/76
CPC分类号： H01L29/66287 , H01L29/1004 , H01L29/66242 , H01L29/732 , H01L29/7378
摘要： A bipolar transistor with raised extrinsic base and selectable self-alignment between the extrinsic base and the emitter is disclosed. The fabrication method may include the formation of a predefined thickness of a first extrinsic base layer of polysilicon or silicon on an intrinsic base. A dielectric landing pad is then formed by lithography on the first extrinsic base layer. Next, a second extrinsic base layer of polysilicon or silicon is formed on top of the dielectric landing pad to finalize the raised extrinsic base total thickness. An emitter opening is formed using lithography and RIE, where the second extrinsic base layer is etched stopping on the dielectric landing pad. The degree of self-alignment between the emitter and the raised extrinsic base is achieved by selecting the first extrinsic base layer thickness, the dielectric landing pad width, and the spacer width.
摘要翻译：公开了一种具有凸起的外在基极和在本征基极和发射极之间可选自对准的双极晶体管。制造方法可以包括在内在基底上形成多晶硅或硅的第一非本征基极层的预定厚度。然后通过在第一非本征基层上的光刻形成电介质着色焊盘。接下来，在电介质贴片垫的顶部上形成第二非多晶硅或硅的非本征基极层，以最终确定凸出的非本征基本总厚度。使用光刻和RIE形成发射器开口，其中第二外部基极层被蚀刻停止在电介质着色焊盘上。通过选择第一非本征基极层厚度，电介质着陆焊盘宽度和间隔物宽度来实现发射极和凸出的外部基极之间的自对准程度。

2. 发明申请

US20070200201A1 STRUCTURE AND METHOD FOR PERFORMANCE IMPROVEMENT IN VERTICAL BIPOLAR TRANSISTORS 有权
标题翻译：垂直双极晶体管性能改进的结构和方法
公开(公告)号：US20070200201A1
公开(公告)日：2007-08-30
申请号：US11741436
申请日：2007-04-27
申请人： James DUNN , David HARAME , Jeffrey JOHNSON , Alvin JOSEPH
发明人： James DUNN , David HARAME , Jeffrey JOHNSON , Alvin JOSEPH
IPC分类号： H01L27/082
CPC分类号： H01L29/7371 , H01L27/0823 , H01L29/66242
摘要： A method of forming a semiconductor device having two different strains therein is provided. The method includes forming a strain in a first region with a first straining film, and forming a second strain in a second region with a second straining film. Either of the first or second strains may be either tensile or compressive. Additionally the strains may be formed at right angles to one another and may be additionally formed in the same region. In particular a vertical tensile strain may be formed in a base and collector region of an NPN bipolar transistor and a horizontal compressive strain may be formed in the extrinsic base region of the NPN bipolar transistor. A PNP bipolar transistor may be formed with a compression strain in the base and collector region in the vertical direction and a tensile strain in the extrinsic base region in the horizontal direction.
摘要翻译：提供了形成其中具有两个不同应变的半导体器件的方法。该方法包括在具有第一应变膜的第一区域中形成应变，并且在第二区域中用第二应变膜形成第二应变。第一或第二应变中的任一种可以是拉伸的或压缩的。此外，菌株可以彼此成直角形成，并且可以另外形成在相同的区域中。特别地，可以在NPN双极晶体管的基极和集电极区域中形成垂直拉伸应变，并且可以在NPN双极晶体管的非本征基极区域中形成水平压缩应变。 PNP双极晶体管可以在垂直方向的基极和集电极区域中形成压缩应变，并且在水平方向上在外部基极区域中形成拉伸应变。

3. 发明申请

US20060249813A1 STRUCTURE AND METHOD FOR PERFORMANCE IMPROVEMENT IN VERTICAL BIPOLAR TRANSISTORS 有权
标题翻译：垂直双极晶体管性能改进的结构和方法
公开(公告)号：US20060249813A1
公开(公告)日：2006-11-09
申请号：US10908361
申请日：2005-05-09
申请人： James Dunn , David Harame , Jeffrey Johnson , Alvin Joseph
发明人： James Dunn , David Harame , Jeffrey Johnson , Alvin Joseph
IPC分类号： H01L27/082
CPC分类号： H01L29/7371 , H01L27/0823 , H01L29/66242
摘要： A method of forming a semiconductor device having two different strains therein is provided. The method includes forming a strain in a first region with a first straining film, and forming a second strain in a second region with a second straining film. Either of the first or second strains may be either tensile or compressive. Additionally the strains may be formed at right angles to one another and may be additionally formed in the same region. In particular a vertical tensile strain may be formed in a base and collector region of an NPN bipolar transistor and a horizontal compressive strain may be formed in the extrinsic base region of the NPN bipolar transistor. A PNP bipolar transistor may be formed with a compression strain in the base and collector region in the vertical direction and a tensile strain in the extrinsic base region in the horizontal direction.
摘要翻译：提供了形成其中具有两个不同应变的半导体器件的方法。该方法包括在具有第一应变膜的第一区域中形成应变，并且在第二区域中用第二应变膜形成第二应变。第一或第二应变中的任一种可以是拉伸的或压缩的。此外，菌株可以彼此成直角形成，并且可以另外形成在相同的区域中。特别地，可以在NPN双极晶体管的基极和集电极区域中形成垂直拉伸应变，并且可以在NPN双极晶体管的非本征基极区域中形成水平压缩应变。 PNP双极晶体管可以在垂直方向的基极和集电极区域中形成压缩应变，并且在水平方向上在外部基极区域中形成拉伸应变。

4. 发明申请

US20080014705A1 STRUCTURE AND METHOD FOR PERFORMANCE IMPROVEMENT IN VERTICAL BIPOLAR TRANSISTORS 有权
标题翻译：垂直双极晶体管性能改进的结构和方法
公开(公告)号：US20080014705A1
公开(公告)日：2008-01-17
申请号：US11760288
申请日：2007-06-08
申请人： James DUNN , David HARAME , Jeffrey JOHNSON , Alvin JOSEPH
发明人： James DUNN , David HARAME , Jeffrey JOHNSON , Alvin JOSEPH
IPC分类号： H01L21/331
CPC分类号： H01L29/7371 , H01L27/0823 , H01L29/66242
摘要： A method of forming a semiconductor device having two different strains therein is provided. The method includes forming a strain in a first region with a first straining film, and forming a second strain in a second region with a second straining film. Either of the first or second strains may be either tensile or compressive. Additionally the strains may be formed at right angles to one another and may be additionally formed in the same region. In particular a vertical tensile strain may be formed in a base and collector region of an NPN bipolar transistor and a horizontal compressive strain may be formed in the extrinsic base region of the NPN bipolar transistor. A PNP bipolar transistor may be formed with a compression strain in the base and collector region in the vertical direction and a tensile strain in the extrinsic base region in the horizontal direction.
摘要翻译：提供了形成其中具有两个不同应变的半导体器件的方法。该方法包括在具有第一应变膜的第一区域中形成应变，并且在第二区域中用第二应变膜形成第二应变。第一或第二应变中的任一种可以是拉伸的或压缩的。此外，菌株可以彼此成直角形成，并且可以另外形成在相同的区域中。特别地，可以在NPN双极晶体管的基极和集电极区域中形成垂直拉伸应变，并且可以在NPN双极晶体管的非本征基极区域中形成水平压缩应变。 PNP双极晶体管可以在垂直方向的基极和集电极区域中形成压缩应变，并且在水平方向上在外部基极区域中形成拉伸应变。

5. 发明申请

US20060081934A1 Bipolar transistor having raised extrinsic base with selectable self-alignment and methods of forming same 失效
标题翻译：双极晶体管具有可选择的自对准的外部基极和其形成方法
公开(公告)号：US20060081934A1
公开(公告)日：2006-04-20
申请号：US11289915
申请日：2005-11-30
申请人： Marwan Khater , James Dunn , David Harame , Alvin Joseph , Qizhi Liu , Francois Pagette , Stephen Onge , Andreas Stricker
发明人： Marwan Khater , James Dunn , David Harame , Alvin Joseph , Qizhi Liu , Francois Pagette , Stephen Onge , Andreas Stricker
IPC分类号： H01L23/62
CPC分类号： H01L29/66287 , H01L29/1004 , H01L29/66242 , H01L29/732 , H01L29/7378
摘要： A bipolar transistor with raised extrinsic base and selectable self-alignment between the extrinsic base and the emitter is disclosed. The fabrication method may include the formation of a predefined thickness of a first extrinsic base layer of polysilicon or silicon on an intrinsic base. A dielectric landing pad is then formed by lithography on the first extrinsic base layer. Next, a second extrinsic base layer of polysilicon or silicon is formed on top of the dielectric landing pad to finalize the raised extrinsic base total thickness. An emitter opening is formed using lithography and RIE, where the second extrinsic base layer is etched stopping on the dielectric landing pad. The degree of self-alignment between the emitter and the raised extrinsic base is achieved by selecting the first extrinsic base layer thickness, the dielectric landing pad width, and the spacer width.
摘要翻译：公开了一种具有凸起的外在基极和在本征基极和发射极之间可选自对准的双极晶体管。制造方法可以包括在内在基底上形成多晶硅或硅的第一非本征基极层的预定厚度。然后通过在第一非本征基层上的光刻形成电介质着色焊盘。接下来，在电介质贴片垫的顶部上形成第二非多晶硅或硅的非本征基极层，以最终确定凸出的非本征基本总厚度。使用光刻和RIE形成发射器开口，其中第二外部基极层被蚀刻停止在电介质着色焊盘上。通过选择第一非本征基极层厚度，电介质着陆焊盘宽度和间隔物宽度来实现发射极和凸出的外部基极之间的自对准程度。

6. 发明申请

US20050054171A1 Incorporation of carbon in silicon/silicon germanium epitaxial layer to enhance yield for Si-Ge bipolar technology 有权
标题翻译：在硅/硅锗外延层中引入碳以提高Si-Ge双极技术的产量
公开(公告)号：US20050054171A1
公开(公告)日：2005-03-10
申请号：US10953378
申请日：2004-09-29
申请人： Jack Chu , Douglas Coolbaugh , James Dunn , David Greenberg , David Harame , Basanth Jagannathan , Robb Johnson , Louis Lanzerotti , Kathryn Schonenberg , Ryan Wuthrich
发明人： Jack Chu , Douglas Coolbaugh , James Dunn , David Greenberg , David Harame , Basanth Jagannathan , Robb Johnson , Louis Lanzerotti , Kathryn Schonenberg , Ryan Wuthrich
IPC分类号： H01L21/331 , H01L29/737 , H01L21/8222
CPC分类号： H01L29/66242 , H01L21/02381 , H01L21/02447 , H01L21/02529 , H01L21/02532 , H01L21/02579 , H01L21/0262 , H01L29/1004 , H01L29/161 , H01L29/7378
摘要： A SiGe bipolar transistor containing substantially no dislocation defects present between the emitter and collector region and a method of forming the same are provided. The SiGe bipolar transistor includes a collector region of a first conductivity type; a SiGe base region formed on a portion of said collector region; and an emitter region of said first conductivity type formed over a portion of said base region, wherein said collector region and said base region include carbon continuously therein. The SiGe base region is further doped with boron.
摘要翻译：提供了在发射极和集电极区域之间基本上不存在位错缺陷的SiGe双极晶体管及其形成方法。 SiGe双极晶体管包括第一导电类型的集电极区域; 形成在所述集电区域的一部分上的SiGe基区; 以及形成在所述基极区域的一部分上的所述第一导电类型的发射极区域，其中所述集电极区域和所述基极区域在其中连续地包括碳。 SiGe基区进一步掺硼。

7. 发明申请

US20050037568A1 Metal-insulator-metal capacitor 失效
标题翻译：金属绝缘体金属电容器
公开(公告)号：US20050037568A1
公开(公告)日：2005-02-17
申请号：US10658036
申请日：2003-09-09
申请人： Nancy Greco , David Harame , Gary Hueckel , Joseph Kocis , Dominique Ngoc , Kenneth Stein
发明人： Nancy Greco , David Harame , Gary Hueckel , Joseph Kocis , Dominique Ngoc , Kenneth Stein
IPC分类号： H01L27/04 , H01L21/02 , H01L21/768 , H01L21/822 , H01L23/522 , H01L21/8242
CPC分类号： H01L23/5223 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： An interconnection wiring system incorporating two levels of interconnection wiring separated by a first dielectric, a capacitor formed by a second dielectric, a bottom electrode of the lower interconnection wiring or a via and a top electrode of the upper interconnection wiring or a separate metal layer. The invention overcomes the problem of leakage current and of substrate stray capacitance by positioning the capacitor between two levels of interconnection wiring.
摘要翻译：一种互连布线系统，包括由第一介质隔离的两层互连布线，由第二介质形成的电容器，下互连布线的底电极或通孔，以及上互连布线的顶电极或单独的金属层。本发明通过将电容器放置在两层互连布线之间来克服漏电流和衬底杂散电容的问题。

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