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1. 发明授权

US06674139B2 Inverse T-gate structure using damascene processing 失效
标题翻译：使用镶嵌加工的逆T型栅结构
公开(公告)号：US06674139B2
公开(公告)日：2004-01-06
申请号：US09910636
申请日：2001-07-20
申请人： Jack A. Mandelman , Carl J. Radens , William R. Tonti
发明人： Jack A. Mandelman , Carl J. Radens , William R. Tonti
IPC分类号： H01L2976
CPC分类号： H01L29/4983 , H01L21/28061 , H01L21/28114 , H01L29/42368 , H01L29/66492 , H01L29/66537 , H01L29/66553 , H01L29/66583 , H01L29/66598 , H01L29/66666
摘要： A field effect transistor has an inverse-T gate conductor having a thicker center portion and thinner wings. The wings may be of a different material different than the center portion. In addition, gate dielectric may be thicker along edges than in the center. Doping can also be different under the wings than along the center portion or beyond the gate. Regions under the wings may be doped differently than the gate conductor. With a substantially vertical implant, a region of the channel overlapped by an edge of the gate is implanted without implanting a center portion of the channel, and this region is blocked from receiving at least a portion of the received by thick portions of the gate electrode.
摘要翻译：场效应晶体管具有具有较厚中心部分和较薄翼的逆T栅极导体。翼可以是与中心部分不同的材料。此外，栅极电介质可以沿着边缘比在中心更厚。翅膀下的掺杂也可以不同于沿着中心部分或超出门。机翼下方的区域可能与栅极导体的掺杂不同。利用基本上垂直的注入，在不注入沟道的中心部分的情况下注入与栅极的边缘重叠的沟道的区域，并且阻止该区域接收栅电极的所接收的较厚部分的至少一部分。

2. 发明授权

US06355531B1 Method for fabricating semiconductor devices with different properties using maskless process 失效
标题翻译：使用无掩模工艺制造具有不同特性的半导体器件的方法
公开(公告)号：US06355531B1
公开(公告)日：2002-03-12
申请号：US09634225
申请日：2000-08-09
申请人： Jack A. Mandelman , Louis L. Hsu , Carl J. Radens , William R. Tonti , Li-Kong Wang
发明人： Jack A. Mandelman , Louis L. Hsu , Carl J. Radens , William R. Tonti , Li-Kong Wang
IPC分类号： H01L218236
CPC分类号： H01L21/823892 , H01L21/823807 , H01L21/82385 , Y10S438/981
摘要： A method is provided for fabricating semiconductor devices having different properties on a common semiconductor substrate. The method includes the steps of (a) forming N openings on the semiconductor substrate, wherein each opening is corresponding to a channel region of each semiconductor device, (b) forming oxide layers of an ith type on surfaces of the N openings, (c) depositing gate conductor material of an ith type over structure of the semiconductor devices, the gate conductor material of the ith type having a gate conductor work-function of an ith type, (d) removing the gate conductor material of the ith type such that a predetermined amount of the gate conductor material of the ith type remains in an ith opening to form a gate conductor material layer of the ith type on top surface in the ith opening and the gate conductor material of the ith type deposited in the structure other than the ith opening is removed, (e) removing the oxide layers of the ith type from openings other than the ith opening, (f) repeating the steps of (a) through (e) from “i=1” to “i=N”, and (g) forming at least one layer on surface of each of N gate conductor material layers in the N openings to form a gate conductor, whereby the N semiconductor devices have N gate conductors, respectively, wherein the N gate conductors have N types of gate conductor work-functions. The semiconductor devices also have channel regions of which doping levels are different from each other by implanting the channel regions with different types of implants.
摘要翻译：提供了一种在公共半导体衬底上制造具有不同特性的半导体器件的方法。该方法包括以下步骤：（a）在半导体衬底上形成N个开口，其中每个开口对应于每个半导体器件的沟道区，（b）在N个开口的表面上形成第i个类型的氧化物层，（c ）沉积所述半导体器件的第i型结构的栅极导体材料，所述第i型栅极导体材料具有第i类型的栅极导体功函数，（d）去除所述第i种类型的栅极导体材料，使得第i个类型的栅极导体材料的预定量保持在第i个开口中，以在第i个开口的顶表面上形成第i型的栅极导体材料层，并且沉积在除第除去第i个开口，（e）从第i个开口以外的开口除去第i个类型的氧化物层，（f）重复步骤（a）至（e）从“i = 1”到“i = N “，（g）在其上形成至少一层在N个开口中的N个栅极导体材料层中的每一个的表面形成栅极导体，由此N个半导体器件分别具有N个栅极导体，其中N个栅极导体具有N种类型的栅极导体功函数。半导体器件还具有通过用不同类型的植入物植入沟道区域而使掺杂水平彼此不同的沟道区域。

3. 发明授权

US06570207B2 Structure and method for creating vertical capacitor and anti-fuse in DRAM process employing vertical array device cell complex 失效
标题翻译：在使用垂直阵列器件单元复合体的DRAM工艺中创建垂直电容器和反熔丝的结构和方法
公开(公告)号：US06570207B2
公开(公告)日：2003-05-27
申请号：US09736496
申请日：2000-12-13
申请人： Louis L. Hsu , Jack A. Mandelman , Carl J. Radens , William R. Tonti
发明人： Louis L. Hsu , Jack A. Mandelman , Carl J. Radens , William R. Tonti
IPC分类号： H01L27108
CPC分类号： H01L27/10897 , H01L23/5252 , H01L27/10841 , H01L27/10864 , H01L27/10894 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit chip is provided having both a conventional DRAM vertical transfer device and an integrated vertical storage capacitor or anti-fuse that can be accessed directly without having to turn on a transfer gate. The mechanism for accessing the integrated capacitor or anti-fuse directly can be a modified doping profile within the vertical cell that provides a low resistance punch-through FET. Alternatively, the mechanism can be a pair of overlapping or nearly overlapping diffusions within the vertical cell.
摘要翻译：提供一种集成电路芯片，其具有常规DRAM垂直传送装置和可以直接访问的集成垂直存储电容器或反熔丝，而不必打开传输门。直接访问集成电容器或反熔丝的机构可以是垂直单元内的修改的掺杂分布，其提供低电阻穿通FET。或者，机构可以是垂直单元内的一对重叠或几乎重叠的扩散。

4. 发明授权

US06538295B1 Salicide device with borderless contact 有权
标题翻译：自杀式装置与无边界接触
公开(公告)号：US06538295B1
公开(公告)日：2003-03-25
申请号：US09645499
申请日：2000-08-25
申请人： Gary B. Bronner , Jeffrey P. Gambino , Louis L. Hsu , Jack A. Mandelman , Carl J. Radens , William R. Tonti
发明人： Gary B. Bronner , Jeffrey P. Gambino , Louis L. Hsu , Jack A. Mandelman , Carl J. Radens , William R. Tonti
IPC分类号： H01L2976
CPC分类号： H01L21/76897 , H01L27/10873 , H01L29/665
摘要： A method and structure for a field effect transistor structure for dynamic random access memory integrated circuit devices has a gate conductor, salicide regions positioned along sides of the gate conductor, a gate cap positioned above the gate conductor and at least one self-aligned contact adjacent the gate conductor.
摘要翻译：用于动态随机存取存储器集成电路器件的场效应晶体管结构的方法和结构具有栅极导体，沿着栅极导体的侧面定位的自对准硅化物区域，位于栅极导体上方的栅极帽和邻近的至少一个自对准接触门导体。

5. 发明授权

US06380027B2 Dual tox trench dram structures and process using V-groove 失效
标题翻译：双毒tox沟结构和工艺采用V型槽
公开(公告)号：US06380027B2
公开(公告)日：2002-04-30
申请号：US09225127
申请日：1999-01-04
申请人： Toshiharu Furukawa , Jeffrey P. Gambino , Edward W. Kiewra , Jack A. Mandelman , Carl J. Radens , William R. Tonti , Mary E. Weybright
发明人： Toshiharu Furukawa , Jeffrey P. Gambino , Edward W. Kiewra , Jack A. Mandelman , Carl J. Radens , William R. Tonti , Mary E. Weybright
IPC分类号： H01L21242
CPC分类号： H01L27/10876 , H01L27/10823 , H01L27/10829 , H01L27/10894
摘要： A structure and method for simultaneously forming array structures and support structures on a substrate comprises forming the array structures to have a V-groove, forming the support structures to have a planar surface, and simultaneously forming a first oxide in the V-groove and a second oxide in the planar surface, wherein the first oxide is thicker than the second oxide.
摘要翻译：用于在衬底上同时形成阵列结构和支撑结构的结构和方法包括：形成阵列结构以具有V形槽，形成支撑结构以具有平坦表面，同时在V形槽中形成第一氧化物，以及其中所述第一氧化物比所述第二氧化物厚。

6. 发明授权

US06174762B1 Salicide device with borderless contact 失效
标题翻译：自杀式装置与无边界接触
公开(公告)号：US06174762B1
公开(公告)日：2001-01-16
申请号：US09260311
申请日：1999-03-02
申请人： Gary B. Bronner , Jeffrey P. Gambino , Louis L. Hsu , Jack A. Mandelman , Carl J. Radens , William R. Tonti
发明人： Gary B. Bronner , Jeffrey P. Gambino , Louis L. Hsu , Jack A. Mandelman , Carl J. Radens , William R. Tonti
IPC分类号： H01L218234
CPC分类号： H01L21/76897 , H01L27/10873 , H01L29/665
摘要： A method and structure for a field effect transistor structure for dynamic random access memory integrated circuit devices has a gate conductor, salicide regions positioned along sides of the gate conductor, a gate cap positioned above the gate conductor and at least one self-aligned contact adjacent the gate conductor.
摘要翻译：用于动态随机存取存储器集成电路器件的场效应晶体管结构的方法和结构具有栅极导体，沿着栅极导体的侧面定位的自对准硅化物区域，位于栅极导体上方的栅极帽和邻近的至少一个自对准接触门导体。

7. 发明授权

US07087948B2 Forming electronic structures having dual dielectric thicknesses and the structure so formed 失效
公开(公告)号：US07087948B2
公开(公告)日：2006-08-08
申请号：US10995444
申请日：2004-11-23
申请人： Louis L. Hsu , Jack A. Mandelman , Carl J. Radens , Richard A. Strub , William R. Tonti
发明人： Louis L. Hsu , Jack A. Mandelman , Carl J. Radens , Richard A. Strub , William R. Tonti
IPC分类号： H01L27/108 , H01L29/76 , H01L29/94 , H01L31/119
CPC分类号： H01L29/66181 , H01L21/823462 , H01L27/10861 , H01L27/10894 , H01L29/945
摘要： A structure including a first device and a second device, wherein the second device has a dielectric thickness greater than the dielectric thickness of the first device, and the method of so forming the structure.

8. 发明授权

US07026202B2 Inverse-T gate structure using damascene processing 失效
标题翻译：逆T门结构使用镶嵌加工
公开(公告)号：US07026202B2
公开(公告)日：2006-04-11
申请号：US10703123
申请日：2003-11-06
申请人： Jack A. Mandelman , Carl J. Radens , William R. Tonti
发明人： Jack A. Mandelman , Carl J. Radens , William R. Tonti
IPC分类号： H01L21/338
CPC分类号： H01L29/4983 , H01L21/28061 , H01L21/28114 , H01L29/42368 , H01L29/66492 , H01L29/66537 , H01L29/66553 , H01L29/66583 , H01L29/66598 , H01L29/66666
摘要： A field effect transistor has an inverse-T gate conductor having a thicker center portion and thinner wings. The wings may be of a different material different than the center portion. In addition, gate dielectric may be thicker along edges than in the center. Doping can also be different under the wings than along the center portion or beyond the gate. Regions under the wings may be doped differently than the gate conductor. With a substantially vertical implant, a region of the channel overlapped by an edge of the gate is implanted without implanting a center portion of the channel, and this region is blocked from receiving at least a portion of the received by thick portions of the gate electrode.
摘要翻译：场效应晶体管具有具有较厚中心部分和较薄翼的逆T栅极导体。翼可以是与中心部分不同的材料。此外，栅极电介质可以沿着边缘比在中心更厚。翅膀下的掺杂也可以不同于沿着中心部分或超出门。机翼下方的区域可能与栅极导体的掺杂不同。利用基本上垂直的注入，在不注入沟道的中心部分的情况下注入与栅极的边缘重叠的沟道的区域，并且阻止该区域接收栅电极的所接收的较厚部分的至少一部分。

9. 发明授权

US06869846B2 Forming electronic structures having dual dielectric thicknesses and the structure so formed 失效
标题翻译：形成具有双介电厚度的电子结构和如此形成的结构
公开(公告)号：US06869846B2
公开(公告)日：2005-03-22
申请号：US10411850
申请日：2003-04-10
申请人： Louis L. Hsu , Jack A. Mandelman , Carl J. Radens , Richard A. Strub , William R. Tonti
发明人： Louis L. Hsu , Jack A. Mandelman , Carl J. Radens , Richard A. Strub , William R. Tonti
IPC分类号： H01L21/8239 , H01L21/334 , H01L21/8234 , H01L21/8242 , H01L29/94
CPC分类号： H01L29/66181 , H01L21/823462 , H01L27/10861 , H01L27/10894 , H01L29/945
摘要： A structure including a first device and a second device, wherein the second device has a dielectric thickness greater than the dielectric thickness of the first device, and the method of so forming the structure.
摘要翻译：一种包括第一装置和第二装置的结构，其中所述第二装置的电介质厚度大于所述第一装置的电介质厚度，以及形成所述结构的方法。

10. 发明授权

US06724029B2 Twin-cell flash memory structure and method 有权
标题翻译：双电池闪存结构及方法
公开(公告)号：US06724029B2
公开(公告)日：2004-04-20
申请号：US09683831
申请日：2002-02-21
申请人： Louis L. Hsu , Chung H. Lam , Jack A. Mandelman , Carl J. Radens , William R. Tonti
发明人： Louis L. Hsu , Chung H. Lam , Jack A. Mandelman , Carl J. Radens , William R. Tonti
IPC分类号： H01L27108
CPC分类号： H01L27/11521 , G11C16/0441 , H01L27/115
摘要： A programmable memory cell structure that includes a pair of memory cells is provided. Each pair of memory cells includes a shared control gate and first and second floating gates present about the shared control gate. The first and second floating gates have respective gate regions disposed on respective sides of the control gate. Dielectric structures are present between the control gate and respective ones of the gate regions of the floating gates. The control gate and gates of the first and second floating gates are formed within a single lithographic square.
摘要翻译：提供了包括一对存储单元的可编程存储单元结构。每对存储单元包括共享控制栅极和围绕共享控制栅极存在的第一和第二浮动栅极。第一和第二浮栅具有设置在控制栅极的相应侧上的各自的栅极区域。电介质结构存在于控制栅极和浮动栅极的各个栅极区域之间。第一和第二浮动栅极的控制栅极和栅极形成在单个光刻平面内。

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