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1. 发明授权

US06748458B2 Modular input/output expansion system for an external computer 失效
标题翻译：用于外部计算机的模块化输入/输出扩展系统
公开(公告)号：US06748458B2
公开(公告)日：2004-06-08
申请号：US09944529
申请日：2001-08-31
申请人： J. Michael Andrewartha , Martha G. Peterson , Farrukh S. Syed , Brent A. Boudreaux , Richard A. Schumacher , Bryan Wayne Pogor , Eric C. Peterson , Lee Thomas VanLanen , Patrick Wesley Clark , Michael Jay Zalta , Scott Stuart Smith , Kirankumar Chhaganlal Patel
发明人： J. Michael Andrewartha , Martha G. Peterson , Farrukh S. Syed , Brent A. Boudreaux , Richard A. Schumacher , Bryan Wayne Pogor , Eric C. Peterson , Lee Thomas VanLanen , Patrick Wesley Clark , Michael Jay Zalta , Scott Stuart Smith , Kirankumar Chhaganlal Patel
IPC分类号： G06F1314
CPC分类号： G06F1/185 , G06F1/181 , G06F1/184 , G06F1/186 , G06F1/189
摘要： The input/output expansion system (“I/O expansion system”) for an external or main computing unit includes a rack; at least one I/O expansion module mounted to the rack, the I/O expansion module comprising at least one I/O circuit card; a utilities control module mounted to the rack, the utilities control module being configured to receive a command from the external computer unit and generating a signal in response to the command for distribution to at least one I/O expansion module; and expansion power chassis mounted to the rack, the an expansion power chassis being electrically connected to a power source and being configured to distribute the power to the at least one I/O expansion module and the utilities control module.
摘要翻译：用于外部或主要计算单元的输入/输出扩展系统（“I / O扩展系统”）包括机架; 至少一个I / O扩展模块安装到所述机架上，所述I / O扩展模块包括至少一个I / O电路卡; 安装到所述机架的公用事业控制模块，所述公用事业控制模块被配置为从所述外部计算机单元接收命令并响应于所述命令分配给至少一个I / O扩展模块而生成信号; 以及扩展电源机箱，其被安装到所述机架，所述扩展电源机箱电连接到电源并且被配置为将所述电力分配给所述至少一个I / O扩展模块和所述公用事业控制模块。

2. 发明申请

US20100131742A1 OUT-OF-ORDER EXECUTION MICROPROCESSOR THAT SELECTIVELY INITIATES INSTRUCTION RETIREMENT EARLY 有权
标题翻译：不合理的执行微处理器，可以选择性地启动指导性的早期恢复
公开(公告)号：US20100131742A1
公开(公告)日：2010-05-27
申请号：US12277409
申请日：2008-11-25
申请人： Gerard M. Col , Brent Bean , Bryan Wayne Pogor
发明人： Gerard M. Col , Brent Bean , Bryan Wayne Pogor
IPC分类号： G06F9/30
CPC分类号： G06F9/3885 , G06F9/3842 , G06F9/3855 , G06F9/3865 , G06F9/3867
摘要： A microprocessor for improving out-of-order superscalar execution unit utilization with a relatively small in-order instruction retirement buffer. A plurality of execution units each calculate an instruction result. The instruction is either an excepting type instruction or a non-excepting type instruction. The excepting type instruction is capable of causing the microprocessor to take an exception after being issued to the execution unit, wherein the non-excepting type instruction is incapable of causing the microprocessor to take an exception after being issued. A retire unit makes a determination that an instruction is the oldest instruction in the microprocessor and that the instruction is ready to update the architectural state of the microprocessor with its result. The retire unit makes the determination before the execution unit outputs the result of the non-excepting type instruction, wherein the retire unit makes the determination after the execution unit outputs the result of the excepting type instruction.
摘要翻译：一种微处理器，用于通过相对较小的订单指令退出缓冲区来改善无序超标量执行单元利用率。多个执行单元各自计算指令结果。该指令是异常类型指令或非除外类型指令。除了类型指令能够使微处理器在发布到执行单元之后发生异常，其中非排除型指令不能使微处理器在发布之后发生异常。退出单元确定指令是微处理器中最早的指令，并且该指令已准备好更新其结果为微处理器的架构状态。退出单元在执行单元输出非除外类型指令的结果之前进行确定，其中退出单元在执行单元输出除外类型指令的结果之后进行确定。

3. 发明申请

US20100306506A1 MICROPROCESSOR WITH SELECTIVE OUT-OF-ORDER BRANCH EXECUTION 有权
标题翻译：具有选择性的超分支执行的微处理器
公开(公告)号：US20100306506A1
公开(公告)日：2010-12-02
申请号：US12582975
申请日：2009-10-21
申请人： Rodney E. Hooker , Gerard M. Col , Bryan Wayne Pogor
发明人： Rodney E. Hooker , Gerard M. Col , Bryan Wayne Pogor
IPC分类号： G06F9/38
CPC分类号： G06F9/3842 , G06F9/3806 , G06F9/3861
摘要： A pipelined out-of-order execution in-order retire microprocessor includes a branch predictor that predicts a target address of a branch instruction, a fetch unit that fetches instructions at the predicted target address, and an execution unit that: resolves a target address of the branch instruction and detects that the predicted and resolved target addresses are different; determines whether there is an unretired instruction that must be corrected and that is older in program order than the branch instruction, in response to detecting that the predicted and resolved target addresses are different; execute the branch instruction by flushing instructions fetched at the predicted target address and causing the fetch unit to fetch from the resolved target address, if there is not an unretired instruction that must be corrected and that is older in program order than the branch instruction; and otherwise, refrain from executing the branch instruction.
摘要翻译：流水线式无序执行按顺序退出微处理器包括预测分支指令的目标地址的分支预测器，取得预测目标地址的指令的获取单元，以及执行单元，其解析目标地址分支指令，并检测预测和解决的目标地址不同; 响应于检测到预测和解析的目标地址不同，确定是否存在必须被校正并且在程序顺序中比分支指令更旧的未命令指令; 通过刷新在预测目标地址处获得的指令来执行分支指令，并且如果不存在必须被校正并且在程序顺序中比分支指令更老的指令，则从解决的目标地址获取提取单元; 否则，不执行分支指令。

4. 发明授权

US08539209B2 Microprocessor that performs a two-pass breakpoint check for a cache line-crossing load/store operation 有权
标题翻译：微处理器执行二次断点检查以进行高速缓存线路交叉加载/存储操作
公开(公告)号：US08539209B2
公开(公告)日：2013-09-17
申请号：US12607301
申请日：2009-10-28
申请人： Bryan Wayne Pogor , Colin Eddy
发明人： Bryan Wayne Pogor , Colin Eddy
IPC分类号： G06F9/312
CPC分类号： G06F11/3648 , G06F12/0802 , G06F12/10
摘要： A microprocessor breakpoint-checks a load/store operation specifying a load/store virtual address of data whose first and second pieces are within first and second cache lines. A queue of entries each include first storage for an address associated with the operation and second storage for an indicator indicating whether there is a match between a page address portion of the virtual address and a page address portion of a breakpoint address. During a first pass through a load/store unit pipeline, the unit performs a first piece breakpoint check using the virtual address, populates the second storage indicator, and populates the first storage with a physical address translated from the virtual address. During the second pass, the unit performs a second piece breakpoint check using the indicator received from the second storage and an incremented version of a page offset portion of the load/store physical address received from the first storage.
摘要翻译：微处理器断点检查装载/存储操作，指定其第一和第二片在第一和第二高速缓存行内的数据的加载/存储虚拟地址。每个条目队列包括用于与该操作相关联的地址的第一存储器和用于指示虚拟地址的寻址地址部分与断点地址的页地址部分之间是否匹配的指示符的第二存储器。在通过加载/存储单元流水线的第一次通过期间，该单元使用虚拟地址执行第一段断点检查，填充第二存储指示符，并用从虚拟地址转换的物理地址填充第一存储器。在第二遍期间，单元使用从第二存储器接收的指示符和从第一存储器接收的加载/存储物理地址的页偏移部分的增量版本来执行第二片断点检查。

5. 发明授权

US08074060B2 Out-of-order execution microprocessor that selectively initiates instruction retirement early 有权
标题翻译：无序执行微处理器能够提前选择性地启动指令退休
公开(公告)号：US08074060B2
公开(公告)日：2011-12-06
申请号：US12277409
申请日：2008-11-25
申请人： Gerard M. Col , Brent Bean , Bryan Wayne Pogor
发明人： Gerard M. Col , Brent Bean , Bryan Wayne Pogor
IPC分类号： G06F9/22 , G06F9/30
CPC分类号： G06F9/3885 , G06F9/3842 , G06F9/3855 , G06F9/3865 , G06F9/3867
摘要： A microprocessor for improving out-of-order superscalar execution unit utilization with a relatively small in-order instruction retirement buffer. A plurality of execution units each calculate an instruction result. The instruction is either an excepting type instruction or a non-excepting type instruction. The excepting type instruction is capable of causing the microprocessor to take an exception after being issued to the execution unit, wherein the non-excepting type instruction is incapable of causing the microprocessor to take an exception after being issued. A retire unit makes a determination that an instruction is the oldest instruction in the microprocessor and that the instruction is ready to update the architectural state of the microprocessor with its result. The retire unit makes the determination before the execution unit outputs the result of the non-excepting type instruction, wherein the retire unit makes the determination after the execution unit outputs the result of the excepting type instruction.
摘要翻译：一种微处理器，用于通过相对较小的订单指令退出缓冲区来改善无序超标量执行单元利用率。多个执行单元各自计算指令结果。该指令是异常类型指令或非除外类型指令。除了类型指令能够使微处理器在发布到执行单元之后发生异常，其中非排除型指令不能使微处理器在发布之后发生异常。退出单元确定指令是微处理器中最早的指令，并且该指令已准备好更新其结果为微处理器的架构状态。退出单元在执行单元输出非除外类型指令的结果之前进行确定，其中退出单元在执行单元输出除外类型指令的结果之后进行确定。

6. 发明授权

US08909908B2 Microprocessor that refrains from executing a mispredicted branch in the presence of an older unretired cache-missing load instruction 有权
标题翻译：在存在较旧的未安装缓存缺失加载指令的情况下，不执行错误预测的分支的微处理器
公开(公告)号：US08909908B2
公开(公告)日：2014-12-09
申请号：US12582975
申请日：2009-10-21
申请人： Rodney E. Hooker , Gerard M. Col , Bryan Wayne Pogor
发明人： Rodney E. Hooker , Gerard M. Col , Bryan Wayne Pogor
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3842 , G06F9/3806 , G06F9/3861
摘要： A pipelined out-of-order execution in-order retire microprocessor includes a branch predictor that predicts a target address of a branch instruction, a fetch unit that fetches instructions at the predicted target address, and an execution unit that: resolves a target address of the branch instruction and detects that the predicted and resolved target addresses are different; determines whether there is an unretired instruction that must be corrected and that is older in program order than the branch instruction, in response to detecting that the predicted and resolved target addresses are different; execute the branch instruction by flushing instructions fetched at the predicted target address and causing the fetch unit to fetch from the resolved target address, if there is not an unretired instruction that must be corrected and that is older in program order than the branch instruction; and otherwise, refrain from executing the branch instruction.
摘要翻译：流水线式无序执行按顺序退出微处理器包括预测分支指令的目标地址的分支预测器，取得预测目标地址的指令的获取单元，以及执行单元，其解析目标地址分支指令，并检测预测和解决的目标地址不同; 响应于检测到预测和解析的目标地址不同，确定是否存在必须被校正并且在程序顺序中比分支指令更旧的未命令指令; 通过刷新在预测目标地址处获得的指令来执行分支指令，并且如果不存在必须被校正并且在程序顺序中比分支指令更老的指令，则从解决的目标地址获取提取单元; 否则，不执行分支指令。

7. 发明授权

US08327119B2 Apparatus and method for executing fast bit scan forward/reverse (BSR/BSF) instructions 有权
标题翻译：执行快速扫描正向/反向（BSR / BSF）指令的装置和方法
公开(公告)号：US08327119B2
公开(公告)日：2012-12-04
申请号：US12582907
申请日：2009-10-21
申请人： Bryan Wayne Pogor
发明人： Bryan Wayne Pogor
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F7/00 , G06F15/00
CPC分类号： G06F9/30018 , G06F9/3017
摘要： An apparatus executes a bit scan instruction that specifies an N-byte input operand. A first encoder forward bit scan encodes each input byte to generate N first bit vectors. A zero detector zero-detects each input byte to generate a second bit vector. A second encoder forward bit scan encodes the second bit vector to generate a third bit vector. An N:1 multiplexor, controlled by the third bit vector, selects one of the N first bit vectors to output a fourth bit vector. The apparatus concatenates the third and fourth bit vectors into a fifth bit vector that indicates the bit index of the least significant set bit of the input operand. A third encoder forward bit scan encodes a bit-reversed version of each input by to generate N sixth bit vectors. A fourth encoder forward bit scan encodes a bit-reversed version of the second bit vector to generate a seventh bit vector. A second N:1 multiplexor, controlled by the seventh bit vector, selects one of the N sixth bit vectors to output an eighth bit vector. Selection logic selects a concatenation of the third and fourth bit vectors into the fifth bit vector if an input indicates forward bit scan, and the selection logic selects an inverted version of a concatenation of the seventh and eighth bit vectors into the fifth bit vector if the input indicates reverse bit scan.
摘要翻译：设备执行指定N字节输入操作数的位扫描指令。第一编码器转发位扫描对每个输入字节进行编码，以产生N个第一位向量。零检测器零检测每个输入字节以产生第二位向量。第二编码器转发位扫描对第二比特向量进行编码以产生第三比特向量。由第三比特向量控制的N：1多路复用器选择N个第一比特向量之一来输出第四比特向量。该装置将第三和第四比特向量连接成指示输入操作数的最低有效集比特的比特索引的第五比特向量。第三编码器转发位扫描通过产生N个第六位向量来编码每个输入的位反转版本。第四编码器转发位扫描对第二位向量的位反转版本进行编码以产生第七位向量。由第七比特向量控制的第二N：1多路复用器选择N个第六比特向量之一来输出第八比特向量。如果输入指示正向位扫描，选择逻辑选择第三位向量和第四位向量的级联到第五位向量中，并且如果选择逻辑选择第七位和第八位向量的级联，则选择逻辑选择第五位向量的级联的反向版本输入表示反向位扫描。

8. 发明授权

US08332618B2 Out-of-order X86 microprocessor with fast shift-by-zero handling 有权
标题翻译：无级处理的X86微处理器具有快速的零位处理能力
公开(公告)号：US08332618B2
公开(公告)日：2012-12-11
申请号：US12634187
申请日：2009-12-09
申请人： Gerard M. Col , Matthew Daniel Day , Terry Parks , Bryan Wayne Pogor
发明人： Gerard M. Col , Matthew Daniel Day , Terry Parks , Bryan Wayne Pogor
IPC分类号： G06F9/315
CPC分类号： G06F9/30032 , G06F9/30094 , G06F9/3838 , G06F9/3855 , G06F9/3857 , G06F9/3861
摘要： An out-of-order execution microprocessor includes a register alias table configured to generate a first indicator that indicates whether an instruction is dependent upon a condition code result of a shift instruction. The microprocessor also includes a first execution unit configured to execute the shift instruction and to generate a second indicator that indicates whether a shift amount of the shift instruction is zero. The microprocessor also includes a second execution unit configured to receive the first and second indicators and to generate a replay signal to cause the instruction to be replayed if the first indicator indicates the instruction is dependent upon the condition code result of the shift instruction and a second indicator indicates the shift amount of the shift instruction is zero.
摘要翻译：无序执行微处理器包括寄存器别名表，其被配置为生成指示指令是否取决于移位指令的条件代码结果的第一指示符。微处理器还包括配置为执行移位指令并产生指示移位指令的移位量是否为零的第二指示符的第一执行单元。微处理器还包括第二执行单元，其被配置为接收第一和第二指示符并产生重播信号以使得如果第一指示符指示指示取决于移位指令的条件代码结果，则使指令重放，而第二执行单元指示器指示移位指令的移位量为零。

9. 发明申请

US20110047314A1 FAST AND EFFICIENT DETECTION OF BREAKPOINTS 有权
标题翻译：快速有效地检测断点
公开(公告)号：US20110047314A1
公开(公告)日：2011-02-24
申请号：US12607301
申请日：2009-10-28
申请人： Bryan Wayne Pogor , Colin Eddy
发明人： Bryan Wayne Pogor , Colin Eddy
IPC分类号： G06F12/08
CPC分类号： G06F11/3648 , G06F12/0802 , G06F12/10
摘要： A microprocessor breakpoint checks a load/store operation specifying a load/store virtual address of data whose first and second pieces are within first and second cache lines. A queue of entries each include first storage for an address associated with the operation and second storage for an indicator indicating whether there is a match between a page address portion of the virtual address and a page address portion of a breakpoint address. During a first pass through a load/store unit pipeline, the unit performs a first piece breakpoint check using the virtual address, populates the second storage indicator, and populates the first storage with a physical address translated from the virtual address. During the second pass, the unit performs a second piece breakpoint check using the indicator received from the second storage and an incremented version of a page offset portion of the load/store physical address received from the first storage.
摘要翻译：微处理器断点检查加载/存储操作，其指定其第一和第二片段在第一和第二高速缓存行内的数据的加载/存储虚拟地址。每个条目队列包括用于与该操作相关联的地址的第一存储器和用于指示虚拟地址的寻址地址部分与断点地址的页地址部分之间是否匹配的指示符的第二存储器。在通过加载/存储单元流水线的第一次通过期间，该单元使用虚拟地址执行第一段断点检查，填充第二存储指示符，并用从虚拟地址转换的物理地址填充第一存储器。在第二遍期间，单元使用从第二存储器接收的指示符和从第一存储器接收的加载/存储物理地址的页偏移部分的增量版本来执行第二片断点检查。

10. 发明申请

US20110035573A1 OUT-OF-ORDER X86 MICROPROCESSOR WITH FAST SHIFT-BY-ZERO HANDLING 有权
标题翻译：使用快速移位零处理的无法使用的X86微处理器
公开(公告)号：US20110035573A1
公开(公告)日：2011-02-10
申请号：US12634187
申请日：2009-12-09
申请人： Gerard M. Col , Matthew Daniel Day , Terry Parks , Bryan Wayne Pogor
发明人： Gerard M. Col , Matthew Daniel Day , Terry Parks , Bryan Wayne Pogor
IPC分类号： G06F9/30
CPC分类号： G06F9/30032 , G06F9/30094 , G06F9/3838 , G06F9/3855 , G06F9/3857 , G06F9/3861
摘要： An out-of-order execution microprocessor includes a register alias table configured to generate a first indicator that indicates whether an instruction is dependent upon a condition code result of a shift instruction. The microprocessor also includes a first execution unit configured to execute the shift instruction and to generate a second indicator that indicates whether a shift amount of the shift instruction is zero. The microprocessor also includes a second execution unit configured to receive the first and second indicators and to generate a replay signal to cause the instruction to be replayed if the first indicator indicates the instruction is dependent upon the condition code result of the shift instruction and a second indicator indicates the shift amount of the shift instruction is zero.
摘要翻译：无序执行微处理器包括寄存器别名表，其被配置为生成指示指令是否取决于移位指令的条件代码结果的第一指示符。微处理器还包括配置为执行移位指令并产生指示移位指令的移位量是否为零的第二指示符的第一执行单元。微处理器还包括第二执行单元，其被配置为接收第一和第二指示符并产生重播信号以使得如果第一指示符指示指示取决于移位指令的条件代码结果，则使指令重放，而第二执行单元指示器指示移位指令的移位量为零。

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