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热词
    • 1. 发明授权
    • Memory apparatus and method capable of setting attribute of information
to be cached
    • 能够设置要缓存的信息的属性的存储装置和方法
    • US5553262A
    • 1996-09-03
    • US231963
    • 1994-04-22
    • Itsuko IshidaMasayuki HataTatsuo Yamada
    • Itsuko IshidaMasayuki HataTatsuo Yamada
    • G06F12/08G06F12/12
    • G06F12/0848G06F12/0846G06F12/0864G06F12/0842G06F12/127G06F2212/601
    • A cache memory apparatus allocates memory regions on the basis of information attributes. The required memory region corresponding to the attribute is accessed before caching is implemented. This enables considerable reduction in apparatus that would otherwise be required to be duplicated among different chips corresponding to the number of information attributes. In a multiple data processing implementation, cache memory regions are allocated for each data processor. The required memory regions of the cache memory are accessed in accordance with information specifying the data processor before caching is carried out. To avoid data collision when the main memory data is substantially rewritten, and when data having the same address and different access types exist simultaneously, data representing the type of access is stored. In response to a change in access, all data signals stored in each ways is nullified so that a plurality of data stored in the memory regions is not simultaneously output.
    • 高速缓存存储装置根据信息属性分配存储区域。 在实现缓存之前访问对应于该属性的所需存储区域。 这使得能够显着地减少否则将需要在对应于信息属性的数量的不同芯片之间复制的装置。 在多重数据处理实现中,为每个数据处理器分配高速缓冲存储器区域。 根据在执行缓存之前指定数据处理器的信息来访问高速缓冲存储器的所需存储区域。 为了在主存储器数据被重写时避免数据冲突,并且当具有相同地址和不同访问类型的数据同时存在时,存储表示访问类型的数据。 响应于访问的变化,以各种方式存储的所有数据信号无效,使得存储在存储器区域中的多个数据不被同时输出。