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1. 发明授权

US5142671A Plural cache architecture for real time multitasking 失效
标题翻译：多重缓存结构，用于实时多任务处理
公开(公告)号：US5142671A
公开(公告)日：1992-08-25
申请号：US434046
申请日：1989-11-09
申请人： Itsuko Ishida , Masayuki Hata , Akira Yamada
发明人： Itsuko Ishida , Masayuki Hata , Akira Yamada
IPC分类号： G06F12/08 , G06F13/36
CPC分类号： G06F12/0842 , G06F12/0811
摘要： In a data processor, when there is any cache memory not being activated after the whole data processor has been activated, a signal is delivered to a bus driver and then a data processing unit is connected to a system bus. During the period from when the whole data processor has been activated to when all the cache memories start to be activated, the data processing unit is connected to the system bus so that data can be transmitted/received between the data processing unit and peripheral devices.
摘要翻译：在数据处理器中，当在整个数据处理器被激活之后没有激活任何高速缓存存储器时，将信号传送到总线驱动器，然后将数据处理单元连接到系统总线。在从整个数据处理器被激活到所有高速缓冲存储器开始被激活的时间段期间，数据处理单元连接到系统总线，以便可以在数据处理单元和外围设备之间发送/接收数据。

2. 发明授权

US5140690A Least-recently-used circuit 失效
标题翻译：最近最少使用的电路
公开(公告)号：US5140690A
公开(公告)日：1992-08-18
申请号：US759643
申请日：1991-09-12
申请人： Masayuki Hata , Akira Yamada
发明人： Masayuki Hata , Akira Yamada
IPC分类号： G06F12/12
CPC分类号： G06F12/125
摘要： A least-recently-used (LRU) circuit determines a replaceable term needed for storing data newly loaded from cache memory for example. The circuit comprises a recently-used information storing means relating to the top priority order or the subordinative order among plural terms, and a least-recently-used determining means for determining which is the top priority term or the subordinative term in accordance with information stored in the recently-used information storing means. High speed processing is thus possible by simplified logical construction. Also, the circuit is provided with control means which directly or indirectly select the predetermined replaceable term, in situations where the determining means cannot properly determine the top-priority replaceable term. Therefore, even when the top-priority replaceable term is selected directly or indirectly, the cache memory can be securely prevented from discontinuing its own functional operation.
摘要翻译：最近最少使用（LRU）电路确定例如存储从缓存存储器新加载的数据所需的可替换术语。电路包括与多个术语中的最高优先顺序或次要顺序有关的最近使用的信息存储装置，以及根据存储的信息确定哪个是最高优先级项或次要术语的最近最近使用的确定装置在最近使用的信息存储装置中。因此，通过简化的逻辑结构可以实现高速处理。此外，在确定装置无法正确地确定最高优先级可替换项的情况下，电路设置有直接或间接选择预定可替换项的控制装置。因此，即使直接或间接选择最优先级可替换项，也可以可靠地防止高速缓冲存储器中止自身的功能操作。

3. 发明授权

US5459852A Cache bypass system with simultaneous initial transfer of target data to both processor and cache 失效
标题翻译：缓存旁路系统，同时将目标数据初始传输到处理器和缓存
公开(公告)号：US5459852A
公开(公告)日：1995-10-17
申请号：US377300
申请日：1995-01-23
申请人： Hiromasa Nakagawa , Akira Yamada , Masayuki Hata
发明人： Hiromasa Nakagawa , Akira Yamada , Masayuki Hata
IPC分类号： G06F12/08 , G06F12/12 , G06F12/06
CPC分类号： G06F12/0879 , G06F12/0859
摘要： A data processor which accesses a memory system only by a block transfer mode for transferring multiple data from the memory system when a cache misses a CPU read-access request for a single data. The data of the address designated by the CPU is read simultaneously into the CPU and cache in parallel from the memory system. After the CPU completes this read-access, the cache is then adapted to continue to read the rest of the multiple data transferred in the block transfer mode. During this time, the CPU does not newly assert an address signal, a bus control signal, and the like but continues to execute its internal processing, such as pipeline processing.
摘要翻译：一种数据处理器，仅当通过块传送模式访问存储器系统，以便在高速缓存未命中单个数据的CPU读取访问请求时从存储器系统传送多个数据。由CPU指定的地址的数据从存储器系统并行读取到CPU中并缓存。在CPU完成该读取访问之后，高速缓存然后适于继续读取以块传送模式传送的多个数据的其余部分。在此期间，CPU不会新建地址信号，总线控制信号等，而是继续执行其内部处理，例如流水线处理。

4. 发明授权

US5638537A Cache system with access mode determination for prioritizing accesses to cache memory 失效
标题翻译：具有访问模式确定优先级高速缓存存储访问的缓存系统
公开(公告)号：US5638537A
公开(公告)日：1997-06-10
申请号：US690401
申请日：1996-07-25
申请人： Akira Yamada , Masayuki Hata , Hiromasa Nakagawa , Koichi Nishida
发明人： Akira Yamada , Masayuki Hata , Hiromasa Nakagawa , Koichi Nishida
IPC分类号： G06F12/08 , G06F113/16
CPC分类号： G06F12/0848 , G06F12/0888
摘要： A cache memory operates in a first mode, in which a cache hit occurs, and in a second mode, in which a cache miss occurs. A data processor operates in a first state in which instructions are accessed from memory and in a second state in which data is accessed from memory. Cache memory has a condition setting circuit which distinguishes instruction caching from a data caching. The processor sends an access-type signal which is compared with the access-type set in the condition setting circuit. When the access-type signal does not coincide with the contents of the condition setting circuit, a third state is declared which links the main memory and cache memory.
摘要翻译：高速缓冲存储器在发生高速缓存命中的第一模式中运行，并且在发生高速缓存未命中的第二模式中操作。数据处理器在其中从存储器访问指令的第一状态和从存储器访问数据的第二状态中操作。缓存存储器具有将指令缓存与数据高速缓存区分开的条件设置电路。处理器发送与条件设置电路中设置的访问类型进行比较的访问类型信号。当访问类型信号与条件设置电路的内容不一致时，声明连接主存储器和高速缓冲存储器的第三状态。

5. 发明授权

US5544341A Data access apparatus for preventing further cache access in case of an error during block data transfer 失效
标题翻译：数据访问装置，用于在块数据传输期间发生错误时防止进一步的高速缓存访问
公开(公告)号：US5544341A
公开(公告)日：1996-08-06
申请号：US454893
申请日：1995-05-31
申请人： Hiromasa Nakagawa , Akira Yamada , Masayuki Hata
发明人： Hiromasa Nakagawa , Akira Yamada , Masayuki Hata
IPC分类号： G06F12/08 , G11C29/00 , G06F13/00 , G06F11/00
CPC分类号： G11C29/88 , G06F12/0879
摘要： A data processor and method for preventing access to a cache memory when an abnormality occurs during a block data transfer. The data processor is provided with a central processing unit (CPU), a memory and the cache which stores a part of the data being stored in the memory. When the data to be accessed by the central processing unit is not stored in the cache, the data processor employs a block transfer method where the central processing unit reads out from the memory a block of data, including a predetermined number of data (words) in which the data to be accessed is located. When an abnormality, such as a parity error, is detected in transferring a data word in the block of data to be accessed, the cache is inhibited from reading another data word in the block to be accessed, and the CPU stops reading out the rest of the block of data to be read out from the memory, so that the central processing unit can immediately take action to respond to the abnormality.
摘要翻译：一种用于在块数据传送期间发生异常时防止对高速缓存存储器的访问的数据处理器和方法。数据处理器设置有中央处理单元（CPU），存储器和存储存储在存储器中的一部分数据的高速缓存。当中央处理单元要访问的数据不存储在高速缓存中时，数据处理器采用块传送方法，其中中央处理单元从存储器读出包括预定数量的数据（字）的数据块，其中要访问的数据位于其中。当在传送要访问的数据块中的数据字中检测到诸如奇偶校验错误的异常时，禁止高速缓存读取要访问的块中的另一个数据字，并且CPU停止读出其余部分的数据块从存储器读出，使得中央处理单元可以立即采取动作来响应异常。

6. 发明授权

US09036535B2 Mobile communication method, radio base station, and relay node to avoid interference in a random access procedure 有权
标题翻译：移动通信方法，无线基站和中继节点，以避免随机接入过程中的干扰
公开(公告)号：US09036535B2
公开(公告)日：2015-05-19
申请号：US13808269
申请日：2011-07-07
申请人： Yasufumi Morioka , Hideaki Takahashi , Yukihiko Okumura , Mikio Iwamura , Akira Yamada
发明人： Yasufumi Morioka , Hideaki Takahashi , Yukihiko Okumura , Mikio Iwamura , Akira Yamada
IPC分类号： H04W74/08 , H04B7/155 , H04W74/00 , H04W84/04 , H04W88/08
CPC分类号： H04W74/0833 , H04B7/155 , H04W74/002 , H04W84/047 , H04W88/08
摘要： A mobile communication method according to the present invention includes a step of transmitting, by a radio base station DeNB, “RA Response” to a mobile station UE within a “RA Response window” for the mobile station UE when “RA Preamble” is received from the mobile station UE, a step of transmitting, by a relay node RN, a signal to the mobile station UE in a subframe other than an MBSFN subframe, and a step of transmitting, by the radio base station DeNB, “RA Response” to the relay node RN in an MBSFN subframe of a “RA Response window” for the relay node RN when “RA Preamble” is received from the relay node RN.
摘要翻译：根据本发明的移动通信方法包括以下步骤：当接收到“RA前导码”时，由无线基站DeNB向移动台UE的“RA响应窗口”内的移动台UE发送“RA响应” 从移动台UE，通过中继节点RN在MBSFN子帧以外的子帧中向移动台UE发送信号的步骤，以及由无线基站DeNB发送“RA响应”的步骤，在从中继节点RN接收到“RA前导码”时，向中继节点RN的“RA响应窗口”的MBSFN子帧中的中继节点RN发送。

7. 发明授权

US08783818B2 Recording apparatus with ultraviolet light irradiation unit 有权
标题翻译：具有紫外线照射单元的记录装置
公开(公告)号：US08783818B2
公开(公告)日：2014-07-22
申请号：US13305651
申请日：2011-11-28
申请人： Akira Yamada , Shinichi Kamoshida
发明人： Akira Yamada , Shinichi Kamoshida
IPC分类号： B41J29/393
CPC分类号： B41J29/393 , B41J11/002
摘要： A recording apparatus including a recording head that discharges UV ink onto a recording material and an ultraviolet light irradiation unit that irradiates ultraviolet light to the discharged UV ink so as to harden the UV ink; further includes a failure diagnostic unit that diagnoses a failure condition of the ultraviolet light irradiation unit and a controller that controls operations of the recording head, the ultraviolet light irradiation unit, and the failure diagnostic unit. Further, the controller is so configured as to change the operation mode of the recording apparatus to a failure-state mode when the ultraviolet light irradiation unit has been diagnosed as a failure by the failure diagnostic unit.
摘要翻译：一种记录装置，包括：将UV油墨排放到记录材料上的记录头;以及紫外光照射单元，其将紫外光照射到排出的UV油墨上，以使UV油墨硬化; 进一步包括诊断紫外线照射单元的故障状态的故障诊断单元和控制记录头，紫外线照射单元和故障诊断单元的操作的控制器。此外，控制器被配置为当紫外线照射单元已经被故障诊断单元诊断为故障时，将记录装置的操作模式改变为故障状态模式。

8. 发明申请

US20130269179A1 INVERTING HEAD 有权
标题翻译：反转头
公开(公告)号：US20130269179A1
公开(公告)日：2013-10-17
申请号：US13995252
申请日：2012-09-11
申请人： Syozo Kadota , Akira Yamada
发明人： Syozo Kadota , Akira Yamada
IPC分类号： H05K3/30
CPC分类号： H05K3/30 , H01L24/75 , H01L2224/7565 , H05K13/0408 , H05K13/0409 , Y10T29/53174
摘要： A nozzle holder 34 includes a nozzle base 51 whose both ends are supported, the nozzle base 51 inside which a vacuum path is formed, extending in a horizontal direction, a nozzle locking member 53 for communicating a nozzle 20a to the vacuum path (vacuum path 72 of the inside of the nozzle base) of the inside of the nozzle base 51, and a pair of fixing members 54 for fixing the nozzle locking member 53 to the nozzle base 51.
摘要翻译：喷嘴保持件34包括两端支撑的喷嘴基座51，在水平方向上形成有真空通路的喷嘴基座51，用于使喷嘴20a与真空通路连通的喷嘴卡止部件（真空通路喷嘴基座51的内侧的喷嘴基部的内侧的72个）以及用于将喷嘴卡定部件53固定在喷嘴基座51上的一对固定部件54。

9. 发明申请

US20130201897A1 BASE STATION, RELAY STATION AND METHOD IN MOBILE COMMUNICATION SYSTEM 有权
标题翻译：基站，移动站和移动通信系统中的方法
公开(公告)号：US20130201897A1
公开(公告)日：2013-08-08
申请号：US13816944
申请日：2011-08-10
申请人： Yasufumi Morioka , Akira Yamada , Junichiro Hagiwara , Hideaki Takahashi , Mikio Iwamura
发明人： Yasufumi Morioka , Akira Yamada , Junichiro Hagiwara , Hideaki Takahashi , Mikio Iwamura
IPC分类号： H04W72/00
CPC分类号： H04W72/005 , H04B7/155 , H04W12/04 , H04W36/0038 , H04W72/042 , H04W84/047
摘要： A base station generates first setting information commonly used for establishing a logical path for communication with a user apparatus and for establishing a logical path for communication with a relay station, and second setting information used only for establishing the logical path for communication with the relay station, and transmits a second RRC message including the second setting information to the relay station after transmitting a first RRC message including the first setting information to the relay station. The first setting information includes information indicating a priority of a radio bearer in the logical path, information indicating usage of resources in SPS, information indicating resources of SRS, configuration information in a MAC sublayer, and information on change of a security encryption key in handover, and the second setting information includes at least system information and MBSFN information.
摘要翻译：基站生成通常用于建立用于与用户装置通信的逻辑路径并建立用于与中继站通信的逻辑路径的第一设置信息，以及仅用于建立用于与中继站通信的逻辑路径的第二设置信息并且在将包括第一设置信息的第一RRC消息发送到中继站之后，向中继站发送包括第二设置信息的第二RRC消息。第一设定信息包括指示逻辑路径中的无线承载的优先级的信息，表示SPS中的资源的使用的信息，指示SRS的资源的信息，MAC子层中的配置信息以及切换中的安全加密密钥的变更的信息并且第二设置信息至少包括系统信息和MBSFN信息。

10. 发明申请

US20130164314A1 CANCER PEPTIDE VACCINE 审中-公开
公开(公告)号：US20130164314A1
公开(公告)日：2013-06-27
申请号：US13808329
申请日：2011-06-30
申请人： Kyogo Itoh , Akira Yamada
发明人： Kyogo Itoh , Akira Yamada
IPC分类号： A61K39/00 , G01N33/68
CPC分类号： A61K39/0011 , A61K2039/545 , A61K2039/55505 , A61K2039/55566 , C07K14/4748 , G01N33/6854
摘要： A composition for treating cancer, comprising 6 to 13 peptides derived from tumor antigens, wherein the composition is used in the manner that antibodies to the respective peptides in the peripheral blood of a patient are measured and peptides to which antibodies are positive are selected and administered to the patient, and a peptide selection method.

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