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1. 发明申请

US20100197130A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20100197130A1
公开(公告)日：2010-08-05
申请号：US12755532
申请日：2010-04-07
申请人： Yoshio OZAWA , Isao Kamioka , Junichi Shiozawa , Akihito Yamamoto , Ryota Fujitsuka , Yoshihiro Ogawa , Katsuaki Natori , Katsuyuki Sekine , Masayuki Tanaka , Daisuke Nishida
发明人： Yoshio OZAWA , Isao Kamioka , Junichi Shiozawa , Akihito Yamamoto , Ryota Fujitsuka , Yoshihiro Ogawa , Katsuaki Natori , Katsuyuki Sekine , Masayuki Tanaka , Daisuke Nishida
IPC分类号： H01L21/336 , H01L21/28
CPC分类号： H01L27/115 , H01L27/11521
摘要： A semiconductor memory device manufacturing method includes forming a floating gate electrode above a semiconductor substrate, forming an interelectrode insulating film above the floating gate electrode, forming a first radical nitride film on a surface of the interelectrode insulating film by first radical nitriding, and forming a control gate electrode on the first radical nitride film.
摘要翻译：一种半导体存储器件制造方法，包括在半导体衬底上形成浮置栅电极，在浮置栅电极上形成电极间绝缘膜，通过第一自由基氮化在电极间绝缘膜的表面上形成第一自由基氮化物膜，第一自由基氮化物膜上的控制栅电极。

2. 发明申请

US20100140682A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：非易失性半导体存储器件及其制造方法
公开(公告)号：US20100140682A1
公开(公告)日：2010-06-10
申请号：US12563651
申请日：2009-09-21
申请人： Isao KAMIOKA , Yoshio OZAWA , Katsuyuki SEKINE
发明人： Isao KAMIOKA , Yoshio OZAWA , Katsuyuki SEKINE
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L29/792 , H01L27/11568 , H01L29/0657 , H01L29/4234 , H01L29/7926
摘要： In a nonvolatile semiconductor memory device, a tunnel insulating layer, a charge storage layer and a charge block layer are formed on a silicon substrate in this order, and a plurality of control gate electrodes are provided above the charge block layer. Moreover, a cap layer made of silicon nitride is formed between the charge block layer and each of the control gate electrode, the cap layer being divided for each gate control electrode.
摘要翻译：在非易失性半导体存储器件中，在硅衬底上依次形成隧道绝缘层，电荷存储层和电荷阻挡层，并且在电荷阻挡层上方设置多个控制栅电极。此外，在电荷阻挡层和控制栅极电极之间形成由氮化硅制成的覆盖层，对于每个栅极控制电极分隔盖层。

3. 发明申请

US20090246932A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20090246932A1
公开(公告)日：2009-10-01
申请号：US12412962
申请日：2009-03-27
申请人： Isao KAMIOKA , Junichi SHIOZAWA , Ryu KATO , Yoshio OZAWA
发明人： Isao KAMIOKA , Junichi SHIOZAWA , Ryu KATO , Yoshio OZAWA
IPC分类号： H01L21/764 , H01L21/28
CPC分类号： H01L29/7881 , H01L21/76208 , H01L27/11521 , H01L29/66825
摘要： A method of manufacturing a semiconductor device according to an embodiment of the present invention includes forming, on a surface of a semiconductor substrate, an isolation trench including sidewall parts and a bottom part, or a stepped structure including a first planar part, a second planar part, and a step part located at a boundary between the first planar part and the second planar part, and supplying oxidizing ions or nitriding ions contained in plasma generated by a microwave, a radio-frequency wave, or electron cyclotron resonance to the sidewall parts and the bottom part of the isolation trench or the first and second planar parts and the step part of the stepped structure by applying a predetermined voltage to the semiconductor substrate, to perform anisotropic oxidation or anisotropic nitridation of the sidewall parts and the bottom part of the isolation trench or the first and second planar parts and the step part of the stepped structure.
摘要翻译：根据本发明实施例的制造半导体器件的方法包括在半导体衬底的表面上形成包括侧壁部分和底部的隔离沟槽，或者包括第一平面部分，第二平面部分部分和位于第一平面部分和第二平面部分之间的边界处的阶梯部分，并且将由微波产生的等离子体中产生的等离子体中的氧离子或氮化离子，射频波或电子回旋共振提供给侧壁部分以及通过向半导体衬底施加预定电压来隔离沟槽的底部或第一和第二平面部分和台阶部分的台阶部分，以进行侧壁部分和底部部分的各向异性氧化或各向异性氮化隔离沟槽或第一和第二平面部分以及台阶结构的阶梯部分。

4. 发明申请

US20090261403A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20090261403A1
公开(公告)日：2009-10-22
申请号：US12406841
申请日：2009-03-18
申请人： Katsuyuki SEKINE , Yoshio OZAWA
发明人： Katsuyuki SEKINE , Yoshio OZAWA
IPC分类号： H01L29/792 , H01L21/28
CPC分类号： H01L29/792 , H01L21/28282 , H01L29/513 , H01L29/66833
摘要： A semiconductor device includes a memory cell transistor including a first lower insulating film provided on a semiconductor substrate, a first intermediate insulating film provided on the first lower insulating film, a first upper insulating film provided on the first intermediate insulating film, and a first gate electrode provided on the first upper insulating film, and a select transistor including a second lower insulating film provided on the semiconductor substrate, a second intermediate insulating film provided on the second lower insulating film, a second upper insulating film provided on the second intermediate insulating film, and a second gate electrode provided on the second upper insulating film, wherein trap density of the second intermediate insulating film is lower than that of the first intermediate insulating film.
摘要翻译：半导体器件包括存储单元晶体管，其包括设置在半导体衬底上的第一下绝缘膜，设置在第一下绝缘膜上的第一中间绝缘膜，设置在第一中间绝缘膜上的第一上绝缘膜和第一栅极设置在第一上绝缘膜上的电极和设置在半导体衬底上的第二下绝缘膜的选择晶体管，设置在第二下绝缘膜上的第二中间绝缘膜，设置在第二中间绝缘膜上的第二上绝缘膜以及设置在第二上绝缘膜上的第二栅电极，其中第二中间绝缘膜的阱密度低于第一中间绝缘膜的陷阱密度。

5. 发明申请

US20080197403A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20080197403A1
公开(公告)日：2008-08-21
申请号：US12026942
申请日：2008-02-06
申请人： Yoshio OZAWA , Akihito Yamamoto , Katsuaki Natori , Masayuki Tanaka , Katsuyuki Sekine , Daisuke Nishida , Ryota Fujitsuka
发明人： Yoshio OZAWA , Akihito Yamamoto , Katsuaki Natori , Masayuki Tanaka , Katsuyuki Sekine , Daisuke Nishida , Ryota Fujitsuka
IPC分类号： H01L27/115
CPC分类号： H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/512 , H01L29/513 , H01L29/66825 , H01L29/7881
摘要： A semiconductor device includes a semiconductor substrate, and nonvolatile memory cells, each of the cells including a channel region having a channel length and a channel width, a tunnel insulating film, a floating gate electrode, a control gate electrode, an inter-electrode insulating film between the floating and control gate electrodes, and an electrode side-wall insulating film on side-wall surfaces of the floating and control gate electrodes, the electrode side-wall insulating film including first and second insulating films having first and second dielectric constants, the first dielectric constant being higher than the second dielectric constant, the second dielectric constant being higher than a dielectric constant of a silicon nitride film, the first insulating film being in a central region of a facing region between the floating and control gate electrodes, the second insulating region being in the both end regions of the facing region and protruding from the both end portions.
摘要翻译：半导体器件包括半导体衬底和非易失性存储单元，每个单元包括具有沟道长度和沟道宽度的沟道区，隧道绝缘膜，浮栅电极，控制栅电极，电极间绝缘在浮置控制栅电极和控制栅极电极的侧壁表面之间的电极侧壁绝缘膜，电极侧壁绝缘膜包括具有第一和第二介电常数的第一和第二绝缘膜，所述第一介电常数高于所述第二介电常数，所述第二介电常数高于氮化硅膜的介电常数，所述第一绝缘膜位于所述浮动栅极和控制栅电极之间的面对区域的中心区域中，第二绝缘区域位于面对区域的两端区域中并从两端口突出 ons。

6. 发明申请

US20080277716A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20080277716A1
公开(公告)日：2008-11-13
申请号：US12113367
申请日：2008-05-01
申请人： Daisuke NISHIDA , Akihito YAMAMOTO , Yoshio OZAWA , Katsuaki NATORI , Katsuyuki SEKINE , Masayuki TANAKA , Ryota FUJITSUKA
发明人： Daisuke NISHIDA , Akihito YAMAMOTO , Yoshio OZAWA , Katsuaki NATORI , Katsuyuki SEKINE , Masayuki TANAKA , Ryota FUJITSUKA
IPC分类号： H01L29/788
CPC分类号： H01L29/7883 , H01L27/115 , H01L27/11521 , H01L29/40114 , H01L29/42324
摘要： A semiconductor device includes a semiconductor substrate having a device formation region, a tunnel insulating film formed on the device formation region, a floating gate electrode formed on the tunnel insulating film, isolation insulating films which cover side surfaces of the device formation region, side surfaces of the tunnel insulating film, and side surfaces of a lower portion of the floating gate electrode, an inter-electrode insulating film which covers an upper surface and side surfaces of an upper portion of the floating gate electrode, and a control gate electrode formed on the inter-electrode insulating film, wherein upper corner portions of the floating gate electrode are rounded as viewed from a direction parallel with the upper surface and the side surfaces of the upper portion of the floating gate electrode.
摘要翻译：半导体器件包括具有器件形成区域的半导体衬底，形成在器件形成区域上的隧道绝缘膜，形成在隧道绝缘膜上的浮置栅电极，覆盖器件形成区域的侧表面的隔离绝缘膜，侧表面的隧道绝缘膜的侧表面和浮栅的下部的侧表面，覆盖浮置栅电极的上部的上表面和侧表面的电极间绝缘膜和形成在栅极电极上的控制栅电极所述电极间绝缘膜，其中，从与所述浮栅电极的上部的上表面和所述侧面平行的方向观察，所述浮栅电极的上角部为圆形。

7. 发明申请

US20110175048A1 NONVOLATILE MEMORY DEVICE AND METHOD FOR MANUFACTURING SAME 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20110175048A1
公开(公告)日：2011-07-21
申请号：US13004287
申请日：2011-01-11
申请人： Katsuyuki SEKINE , Ryota FUJITSUKA , Yoshio OZAWA
发明人： Katsuyuki SEKINE , Ryota FUJITSUKA , Yoshio OZAWA
IPC分类号： H01L45/00 , H01L21/02
CPC分类号： H01L45/1273 , H01L27/2409 , H01L27/2481 , H01L45/08 , H01L45/1226 , H01L45/1233 , H01L45/146 , H01L45/16
摘要： According to one embodiment, a nonvolatile memory device includes first and second conductive layers, a resistance change layer, and a rectifying element. The first conductive layer has first and second major surfaces. The second conductive layer has third and fourth major surfaces, a side face, and a corner part. The third major surface faces the first major surface and includes a plane parallel to the first major face and is provided between the fourth and first major surfaces. The corner part is provided between the third major surface and the side face. The corner part has a curvature higher than that of the third major surface. The resistance change layer is provided between the first and second conductive layers. The rectifying element faces the second major surface of the first conductive layer. An area of the third major surface is smaller than that the second major surface.
摘要翻译：根据一个实施例，非易失性存储器件包括第一和第二导电层，电阻变化层和整流元件。第一导电层具有第一和第二主表面。第二导电层具有第三和第四主表面，侧面和拐角部分。第三主表面面向第一主表面并且包括平行于第一主面的平面，并且设置在第四主表面和第一主表面之间。角部设置在第三主表面和侧面之间。角部具有高于第三主表面的曲率。电阻变化层设置在第一和第二导电层之间。整流元件面向第一导电层的第二主表面。第三主表面的面积小于第二主表面的面积。

8. 发明申请

US20100237402A1 SEMICONDUCTOR MEMORY DEVICE HAVING THREE-DIMENSIONALLY ARRANGED MEMORY CELLS, AND MANUFACTURING METHOD THEREOF 有权
标题翻译：具有三维方向记忆细胞的半导体存储器件及其制造方法
公开(公告)号：US20100237402A1
公开(公告)日：2010-09-23
申请号：US12726952
申请日：2010-03-18
申请人： Katsuyuki SEKINE , Kensuke TAKANO , Masaaki HIGUCHI , Tetsuya KAI , Yoshio OZAWA
发明人： Katsuyuki SEKINE , Kensuke TAKANO , Masaaki HIGUCHI , Tetsuya KAI , Yoshio OZAWA
IPC分类号： H01L29/792 , H01L21/336
CPC分类号： H01L27/11578 , H01L27/11551 , H01L27/11556 , H01L27/11582 , H01L29/42332 , H01L29/7881 , H01L29/792 , H01L29/7926
摘要： A first select transistor is formed on a semiconductor substrate. Memory cell transistors are stacked on the first select transistor and connected in series. A second select transistor is formed on the memory cell transistors. The memory cell transistors include a tapered semiconductor pillar which increases in diameter from the first select transistor toward the second select transistor, a tunnel dielectric film formed on the side surface of the semiconductor pillar, a charge storage layer which is formed on the side surface of the tunnel dielectric film and which increases in charge trap density from the first select transistor side toward the second select transistor side, a block dielectric film formed on the side surface of the charge storage layer, and conductor films which are formed on the side surface of the block dielectric film and which serve as gate electrodes.
摘要翻译：第一选择晶体管形成在半导体衬底上。存储单元晶体管堆叠在第一选择晶体管上并串联连接。在存储单元晶体管上形成第二选择晶体管。存储单元晶体管包括从第一选择晶体管朝向第二选择晶体管的直径增加的锥形半导体柱，形成在半导体柱的侧表面上的隧道电介质膜，形成在半导体柱的侧表面上的电荷存储层隧道电介质膜，并且其从第一选择晶体管侧朝向第二选择晶体管侧的电荷陷阱密度增加，形成在电荷存储层的侧表面上的块状电介质膜和形成在电荷存储层的侧表面上的导体膜该块介质膜并用作栅电极。

9. 发明申请

US20090134446A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20090134446A1
公开(公告)日：2009-05-28
申请号：US12275995
申请日：2008-11-21
申请人： Katsuyuki SEKINE , Yoshio OZAWA , Hiroaki TSUNODA
发明人： Katsuyuki SEKINE , Yoshio OZAWA , Hiroaki TSUNODA
IPC分类号： H01L29/788 , H01L29/68 , H01L29/66
CPC分类号： H01L29/7881 , H01L27/115 , H01L27/11521 , H01L27/11568 , H01L29/42336 , H01L29/511
摘要： A semiconductor device includes a tunnel insulating film formed on a semiconductor substrate, a floating gate electrode formed on the tunnel insulating film, an inter-electrode insulating film formed on the floating gate electrode, and a control gate electrode formed on the inter-electrode insulating film, wherein the inter-electrode insulating film includes a main insulating film and a plurality of nano-particles in the main insulating film.
摘要翻译：半导体器件包括形成在半导体衬底上的隧道绝缘膜，形成在隧道绝缘膜上的浮栅电极，形成在浮栅电极上的电极间绝缘膜，以及形成在电极间绝缘层上的控制栅电极膜，其中所述电极间绝缘膜包括主绝缘膜和所述主绝缘膜中的多个纳米颗粒。

10. 发明申请

US20110140068A1 RESISTANCE-CHANGE MEMORY CELL ARRAY 有权
标题翻译：电阻变化记忆细胞阵列
公开(公告)号：US20110140068A1
公开(公告)日：2011-06-16
申请号：US12941434
申请日：2010-11-08
申请人： Yoshio OZAWA , Katsuyuki Sekine
发明人： Yoshio OZAWA , Katsuyuki Sekine
IPC分类号： H01L27/24
CPC分类号： H01L27/2418 , H01L27/249 , H01L45/04 , H01L45/06 , H01L45/08 , H01L45/085 , H01L45/1226 , H01L45/1266 , H01L45/146 , H01L45/149
摘要： According to one embodiment, a resistance-change memory cell array in which a plurality of horizontal electrodes extending horizontally and a plurality of vertical electrodes extending vertically are arranged to configure a cross-point structure includes rectifying insulating films formed in contact with side surfaces of the vertical electrodes in facing regions between the horizontal electrodes and the vertical electrodes, variable resistance films formed in contact with side surfaces of the horizontal electrodes in the facing regions between the horizontal electrodes and the vertical electrodes, and conductive layers formed between the rectifying insulating films and the variable resitstance films.
摘要翻译：根据一个实施例，其中布置有水平延伸的多个水平电极和垂直延伸的多个垂直电极的电阻变化存储单元阵列被布置为构成交叉点结构，包括与所述第一表面的侧表面接触形成的整流绝缘膜在水平电极和垂直电极之间的面对区域中的垂直电极，在水平电极和垂直电极之间的相对区域中与水平电极的侧表面接触形成的可变电阻膜，以及形成在整流绝缘膜和可变电影片。

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