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1. 发明授权

US06905921B1 Advanced MOSFET design 失效
标题翻译：先进的MOSFET设计
公开(公告)号：US06905921B1
公开(公告)日：2005-06-14
申请号：US10800259
申请日：2004-03-11
申请人： Yowjuang (Bill) Liu , Francois Gregoire
发明人： Yowjuang (Bill) Liu , Francois Gregoire
IPC分类号： H01L21/265 , H01L21/336 , H01L29/76 , H01L29/78 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/66492 , H01L21/26513 , H01L29/6659 , H01L29/7833
摘要： The present invention includes an advanced MOSFET design and manufacturing approach that allow further increase in IC packing density by appropriately addressing the increased leakage problems associated with it. The MOSFET according to one embodiment of the present invention includes a gate, source/drain diffusion regions on opposite sides of the gate, and source/drain extensions adjacent the source/drain diffusion regions. The MOSFET also includes at least one added corner diffusion region that overlaps with at least a portion of a source/drain extension region for reducing off-state leakage currents. The corner diffusions can be created using conventional CMOS IC fabrication processes with some modification of an ion implant mask used in manufacturing a conventional CMOS IC.
摘要翻译：本发明包括先进的MOSFET设计和制造方法，通过适当地解决与之相关的增加的泄漏问题，可以进一步提高IC封装密度。根据本发明的一个实施例的MOSFET包括在栅极的相对侧上的栅极，源极/漏极扩散区域以及与源极/漏极扩散区域相邻的源极/漏极延伸部分。 MOSFET还包括与源极/漏极延伸区域的至少一部分重叠的至少一个添加的拐角扩散区域，用于减少截止状态的漏电流。可以使用传统的CMOS IC制造工艺创建拐角扩散，同时对用于制造常规CMOS IC的离子注入掩模进行一些修改。

2. 发明授权

US06974998B1 Field effect transistor with corner diffusions for reduced leakage 失效
标题翻译：具有拐角扩散的场效应晶体管用于减少泄漏
公开(公告)号：US06974998B1
公开(公告)日：2005-12-13
申请号：US10247218
申请日：2002-09-19
申请人： Yowjuang (Bill) Liu , Francois Gregoire
发明人： Yowjuang (Bill) Liu , Francois Gregoire
IPC分类号： H01L21/265 , H01L21/336 , H01L29/76 , H01L29/78 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/66492 , H01L21/26513 , H01L29/6659 , H01L29/7833
摘要： The present invention includes an advanced MOSFET design and manufacturing approach that allow further increase in IC packing density by appropriately addressing the increased leakage problems associated with it. The MOSFET according to one embodiment of the present invention includes a gate, source/drain diffusion regions on opposite sides of the gate, and source/drain extensions adjacent the source/drain diffusion regions. The MOSFET also includes at least one added corner diffusion region that overlaps with at least a portion of a source/drain extension region for reducing off-state leakage currents. The corner diffusions can be created using conventional CMOS IC fabrication processes with some modification of an ion implant mask used in manufacturing a conventional CMOS IC.
摘要翻译：本发明包括先进的MOSFET设计和制造方法，通过适当地解决与之相关的增加的泄漏问题，可以进一步提高IC封装密度。根据本发明的一个实施例的MOSFET包括在栅极的相对侧上的栅极，源极/漏极扩散区域和与源极/漏极扩散区域相邻的源极/漏极延伸部分。 MOSFET还包括与源极/漏极延伸区域的至少一部分重叠的至少一个添加的拐角扩散区域，用于减少截止状态的漏电流。可以使用传统的CMOS IC制造工艺创建拐角扩散，同时对用于制造常规CMOS IC的离子注入掩模进行一些修改。

3. 发明授权

US07235884B1 Local control of electrical and mechanical properties of copper interconnects to achieve stable and reliable via 有权
标题翻译：局部控制铜互连的电气和机械性能，实现稳定可靠的通孔
公开(公告)号：US07235884B1
公开(公告)日：2007-06-26
申请号：US10405856
申请日：2003-04-01
申请人： Peter John McElheny , Yow-Juang(Bill) W. Liu , Jayakannan Jayapalan , Francois Gregoire
发明人： Peter John McElheny , Yow-Juang(Bill) W. Liu , Jayakannan Jayapalan , Francois Gregoire
IPC分类号： H01L23/48
CPC分类号： H01L23/53295 , H01L21/76814 , H01L21/76886 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： The present invention is a novel method whereby voids or solid opens at the bottom of via can be avoided without drastically altering the resistivity or parasitic capacitances of the whole metal interconnect system. The invention includes in one embodiment a process of forming interconnects and vias in a microelectronic circuit structure. This process includes implanting and/or alloying an impurity element in the local area of the top surface of a metal interconnect at the bottom of a via. Doping may be done before or after formation of the via. After the via is formed, it is filled with a metal such as copper. Another embodiment of the invention is a microelectronic circuit structure manufactured by the aforementioned method.
摘要翻译：本发明是一种新颖的方法，可以避免通孔底部的空隙或固体开放，而不会显着改变整个金属互连系统的电阻率或寄生电容。本发明在一个实施例中包括在微电子电路结构中形成互连和通孔的工艺。该过程包括在通孔底部的金属互连的顶表面的局部区域中植入和/或合金杂质元素。兴奋剂可以在通孔形成之前或之后进行。在通孔形成之后，其被诸如铜的金属填充。本发明的另一实施例是通过上述方法制造的微电子电路结构。

4. 发明申请

US20050003601A1 Polysilicon gate doping level variation for reduced leakage current 有权
标题翻译：多晶硅栅掺杂电平变化，减少漏电流
公开(公告)号：US20050003601A1
公开(公告)日：2005-01-06
申请号：US10830359
申请日：2004-04-22
申请人： Peter McElheny , Priya Selvaraj , Yow-Juang Liu , Francois Gregoire
发明人： Peter McElheny , Priya Selvaraj , Yow-Juang Liu , Francois Gregoire
IPC分类号： H01L21/8238 , H01L21/3205
CPC分类号： H01L21/823842
摘要： A method for fabricating a transistor on a semiconductor substrate includes varying a polysilicon doping level near a first and second edge of a diffusion region with a polysilicon doping level of a center region of a polysilicon region.
摘要翻译：一种用于在半导体衬底上制造晶体管的方法包括：在多晶硅区域的中心区域的多晶硅掺杂水平下改变扩散区域的第一和第二边缘附近的多晶硅掺杂水平。

5. 发明授权

US06750106B2 Polysilicon gate doping level variation for reduced leakage current 有权
标题翻译：多晶硅栅掺杂电平变化，减少漏电流
公开(公告)号：US06750106B2
公开(公告)日：2004-06-15
申请号：US10156267
申请日：2002-05-28
申请人： Peter McElheny , Priya Selvaraj , Bill Liu , Francois Gregoire
发明人： Peter McElheny , Priya Selvaraj , Bill Liu , Francois Gregoire
IPC分类号： H01L218234
CPC分类号： H01L21/823842
摘要： A method of fabricating transistors on a semiconductor substrate is disclosed according to a first embodiment of the present invention. Gate dielectrics of equal thickness are provided to a first and second transistor on the semiconductor substrate. A polysilicon doping level of the first transistor is varied with a polysilicon doping level of the second transistor.
摘要翻译：根据本发明的第一实施例公开了一种在半导体衬底上制造晶体管的方法。相同厚度的栅极电介质被提供给半导体衬底上的第一和第二晶体管。第一晶体管的多晶硅掺杂水平随着第二晶体管的多晶硅掺杂水平而变化。

6. 发明授权

US07045427B2 Polysilicon gate doping level variation for reduced leakage current 有权
标题翻译：多晶硅栅掺杂电平变化，减少漏电流
公开(公告)号：US07045427B2
公开(公告)日：2006-05-16
申请号：US10830359
申请日：2004-04-22
申请人： Peter McElheny , Priya Selvaraj , Yow-Juang (Bill) Liu , Francois Gregoire
发明人： Peter McElheny , Priya Selvaraj , Yow-Juang (Bill) Liu , Francois Gregoire
IPC分类号： H01L21/8234
CPC分类号： H01L21/823842
摘要： A method for fabricating a transistor on a semiconductor substrate includes varying a polysilicon doping level near a first and second edge of a diffusion region with a polysilicon doping level of a center region of a polysilicon region.
摘要翻译：一种用于在半导体衬底上制造晶体管的方法包括：在多晶硅区域的中心区域的多晶硅掺杂水平下改变扩散区域的第一和第二边缘附近的多晶硅掺杂水平。

7. 发明授权

US06829127B1 High performance capacitor structure 失效
标题翻译：高性能电容器结构
公开(公告)号：US06829127B1
公开(公告)日：2004-12-07
申请号：US10383133
申请日：2003-03-05
申请人： Yow-Juang (Bill) Liu , Jayakannan Jayapalan , Francois Gregoire , Peter John McElheny
发明人： Yow-Juang (Bill) Liu , Jayakannan Jayapalan , Francois Gregoire , Peter John McElheny
IPC分类号： H02H300
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11558 , H01L28/90 , H01L29/945
摘要： A capacitive electrode structure for use in an integrated circuit fabricated on a substrate comprises a first electrode formed by a diffusion region in the substrate, an insulating layer formed on the diffusion region, and a second electrode formed by a conductive layer deposited on said insulating layer. To increase the capacitance per chip area of the capacitive electrode structure, a plurality of recesses are formed in the first electrode on an upper surface thereof with a lower surface of the second electrode substantially following a contour of these recesses. In one embodiment, the capacitive electrode structure is employed for a capacitor formed between a control gate and a floating gate in an EEPROM cell. Capacitors in other types of integrated circuit can be likewise formed using the electrode structure of the present invention. Preferably, the recesses in the diffusion region are formed concurrently with oxide-filled isolation trenches in the substrate used to isolate adjacent circuit elements from each other.
摘要翻译：用于制造在衬底上的集成电路中的电容电极结构包括由衬底中的扩散区形成的第一电极，形成在扩散区上的绝缘层，以及由沉积在所述绝缘层上的导电层形成的第二电极。为了增加电容电极结构的每个芯片面积的电容，在其上表面上的第一电极中形成多个凹槽，其中第二电极的下表面大致遵循这些凹槽的轮廓。在一个实施例中，电容电极结构用于形成在EEPROM单元中的控制栅极和浮置栅极之间的电容器。可以使用本发明的电极结构同样地形成其他类型的集成电路中的电容器。优选地，扩散区域中的凹部与用于将相邻电路元件彼此隔离的衬底中的氧化物填充隔离沟槽同时形成。

8. 发明授权

US5939790A Integrated circuit pad structures 失效
标题翻译：集成电路板结构
公开(公告)号：US5939790A
公开(公告)日：1999-08-17
申请号：US631667
申请日：1996-04-09
申请人： Francois Gregoire , Raminda Madurawe , Guru Thalapaneni
发明人： Francois Gregoire , Raminda Madurawe , Guru Thalapaneni
IPC分类号： H01L23/485 , H01L23/48 , H01L21/60
CPC分类号： H01L24/05 , H01L2224/05093 , H01L2224/05095 , H01L2224/05556 , H01L2224/05624 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/05042 , H01L2924/14
摘要： Pad structures for an integrated circuit are provided that use via holes or slots rather than large pad openings to form electrical connections between successive metal interconnection layers. The via holes or slots are filled using standard metal etchback deposition techniques. The pad structures minimize particle generation during circuit fabrication. A number of the via holes or slots in the pad structure can be interconnected in parallel to provide a sufficient current handling capacity to distribute power to the active components on the integrated circuit.
摘要翻译：提供了用于集成电路的焊盘结构，其使用通孔或狭槽而不是大的焊盘开口以在连续的金属互连层之间形成电连接。使用标准金属回蚀沉积技术填充通孔或槽。焊盘结构使电路制造过程中的颗粒产生最小化。焊盘结构中的多个通孔或槽可以并联连接以提供足够的电流处理能力以将功率分配给集成电路上的有源部件。

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