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1. 发明申请

US20150021738A1 BIPOLAR JUNCTION TRANSISTORS WITH AN AIR GAP IN THE SHALLOW TRENCH ISOLATION 有权
标题翻译：带有空气隙的双极接头晶体管在浅层隔离分离器中
公开(公告)号：US20150021738A1
公开(公告)日：2015-01-22
申请号：US13946379
申请日：2013-07-19
申请人： International Business Machines Corporation
发明人： Renata Camillo-Castillo , Vibhor Jain , Vikas K. Kaushal , Marwan H. Khater , Anthony K. Stamper
IPC分类号： H01L29/735 , H01L29/66
CPC分类号： H01L29/66242 , H01L29/0649 , H01L29/0826 , H01L29/1004 , H01L29/7378
摘要： Device structures, fabrication methods, and design structures for a bipolar junction transistor. A trench isolation region is formed in a substrate. The trench isolation region is coextensive with a collector in the substrate. A base layer is formed on the collector and on a first portion of the trench isolation region. A dielectric layer is formed on the base layer and on a second portion of the trench isolation region peripheral to the base layer. After the dielectric layer is formed, the trench isolation region is at least partially removed to define an air gap beneath the dielectric layer and the base layer.
摘要翻译：双极结型晶体管的器件结构，制造方法和设计结构。在衬底中形成沟槽隔离区。沟槽隔离区域与衬底中的集电极共同延伸。基底层形成在集电器和沟槽隔离区的第一部分上。电介质层形成在基底层上和在基底层周边的沟槽隔离区域的第二部分上。在形成电介质层之后，至少部分去除沟槽隔离区域以在电介质层和基底层下方形成气隙。

2. 发明授权

US08810005B1 Bipolar device having a monocrystalline semiconductor intrinsic base to extrinsic base link-up region 有权
标题翻译：双极器件具有单晶半导体本征基极到外部基极连接区域
公开(公告)号：US08810005B1
公开(公告)日：2014-08-19
申请号：US13782094
申请日：2013-03-01
申请人： International Business Machines Corporation
发明人： Renata A. Camillo-Castillo , Peng Cheng , Peter B. Gray , Vibhor Jain , Vikas K. Kaushal , Marwan H. Khater
IPC分类号： H01L29/66 , H01L29/10 , H01L29/737 , H01L29/732
CPC分类号： H01L29/66242 , H01L29/04 , H01L29/0649 , H01L29/1004 , H01L29/66287 , H01L29/732 , H01L29/7378
摘要： A bipolar device with an entirely monocrystalline intrinsic base to extrinsic base link-up region. To form the device, a first extrinsic base layer, which is amorphous or polycrystalline, is deposited such that it contacts an edge portion of a monocrystalline section of an intrinsic base layer through an opening in a dielectric layer. A second extrinsic base layer is deposited on the first. An anneal is performed, either before or after deposition of the second extrinsic base layer, so that the extrinsic base layers are monocrystalline. An opening is formed through the extrinsic base layers to a dielectric landing pad aligned above a center portion of the monocrystalline section of the intrinsic base layer. The dielectric landing pad is removed and a semiconductor layer is grown epitaxially on exposed monocrystalline surfaces of the extrinsic and intrinsic base layers, thereby forming the entirely monocrystalline intrinsic base to extrinsic base link-up region.
摘要翻译：具有完全单晶内在基极的外在基极连接区域的双极器件。为了形成器件，沉积非晶或多晶的第一非本征基层，使得其通过介电层中的开口接触本征基极层的单晶部分的边缘部分。第二个外在基层沉积在第一个外基层上。在第二非本征基层沉积之前或之后进行退火，使得外部基极层是单晶的。通过外部基极层形成开口，形成在本征基极层的单晶部分的中心部分上方的电介质着色垫。去除电介质着陆焊盘并在外部和本征基极层的暴露的单晶表面上外延生长半导体层，从而形成完全单晶内在碱基到外在碱基连接区。

3. 发明授权

US09070734B2 Heterojunction bipolar transistors with reduced parasitic capacitance 有权
公开(公告)号：US09070734B2
公开(公告)日：2015-06-30
申请号：US14528388
申请日：2014-10-30
申请人： International Business Machines Corporation
发明人： Renata Camillo-Castillo , Vibhor Jain , Vikas K. Kaushal , Marwan H. Khater
IPC分类号： H01L29/66 , H01L27/082 , H01L21/331 , H01L29/737 , H01L29/10 , H01L29/08
CPC分类号： H01L29/737 , H01L29/0649 , H01L29/0817 , H01L29/0821 , H01L29/0826 , H01L29/1004 , H01L29/66242 , H01L29/7371 , H01L29/7378
摘要： Fabrication methods, device structures, and design structures for a heterojunction bipolar transistor. A trench isolation region and a collector are formed in a semiconductor substrate. The collector is coextensive with the trench isolation region. A first semiconductor layer is formed that includes a of single crystal section disposed on the collector and on the trench isolation region. A second semiconductor layer is formed that includes a single crystal section disposed on the single crystal section of the first semiconductor layer and that has an outer edge that overlies the trench isolation region. The section of the first semiconductor layer has a second width greater than a first width of the collector. The section of the second semiconductor layer has a third width greater than the second width. A cavity extends laterally from the outer edge of section of the second semiconductor layer to the section of the first semiconductor layer.

4. 发明申请

US20150053982A1 HETEROJUNCTION BIPOLAR TRANSISTORS WITH REDUCED PARASITIC CAPACITANCE 有权
公开(公告)号：US20150053982A1
公开(公告)日：2015-02-26
申请号：US14528388
申请日：2014-10-30
申请人： International Business Machines Corporation
发明人： Renata Camillo-Castillo , Vibhor Jain , Vikas K. Kaushal , Marwan H. Khater
IPC分类号： H01L29/737 , H01L29/08 , H01L29/10
CPC分类号： H01L29/737 , H01L29/0649 , H01L29/0817 , H01L29/0821 , H01L29/0826 , H01L29/1004 , H01L29/66242 , H01L29/7371 , H01L29/7378
摘要： Fabrication methods, device structures, and design structures for a heterojunction bipolar transistor. A trench isolation region and a collector are formed in a semiconductor substrate. The collector is coextensive with the trench isolation region. A first semiconductor layer is formed that includes a of single crystal section disposed on the collector and on the trench isolation region. A second semiconductor layer is formed that includes a single crystal section disposed on the single crystal section of the first semiconductor layer and that has an outer edge that overlies the trench isolation region. The section of the first semiconductor layer has a second width greater than a first width of the collector. The section of the second semiconductor layer has a third width greater than the second width. A cavity extends laterally from the outer edge of section of the second semiconductor layer to the section of the first semiconductor layer.

5. 发明授权

US08957456B1 Heterojunction bipolar transistors with reduced parasitic capacitance 有权
标题翻译：具有降低的寄生电容的异质结双极晶体管
公开(公告)号：US08957456B1
公开(公告)日：2015-02-17
申请号：US13955382
申请日：2013-07-31
申请人： International Business Machines Corporation
发明人： Renata Camillo-Castillo , Vibhor Jain , Vikas K. Kaushal , Marwan H. Khater
IPC分类号： H01L29/66 , H01L21/336 , H01L21/20 , H01L29/737 , G06F17/50
CPC分类号： H01L29/737 , H01L29/0649 , H01L29/0817 , H01L29/0821 , H01L29/0826 , H01L29/1004 , H01L29/66242 , H01L29/7371 , H01L29/7378
摘要： Fabrication methods, device structures, and design structures for a heterojunction bipolar transistor. A trench isolation region and a collector are formed in a semiconductor substrate. The collector is coextensive with the trench isolation region. A first semiconductor layer is formed that includes a of single crystal section disposed on the collector and on the trench isolation region. A second semiconductor layer is formed that includes a single crystal section disposed on the single crystal section of the first semiconductor layer and that has an outer edge that overlies the trench isolation region. The section of the first semiconductor layer has a second width greater than a first width of the collector. The section of the second semiconductor layer has a third width greater than the second width. A cavity extends laterally from the outer edge of section of the second semiconductor layer to the section of the first semiconductor layer.
摘要翻译：异质结双极晶体管的制造方法，器件结构和设计结构。在半导体衬底中形成沟槽隔离区和集电极。收集器与沟槽隔离区域共同延伸。形成第一半导体层，其包括设置在集电极和沟槽隔离区上的单晶部分。形成第二半导体层，其包括设置在第一半导体层的单晶部分上并具有覆盖在沟槽隔离区域上的外边缘的单晶部分。第一半导体层的截面具有大于集电体的第一宽度的第二宽度。第二半导体层的截面具有大于第二宽度的第三宽度。空腔从第二半导体层的截面的外边缘横向延伸到第一半导体层的部分。

6. 发明申请

US20140264341A1 BIPOLAR JUNCTION TRANSISTORS WITH REDUCED EPITAXIAL BASE FACETS EFFECT FOR LOW PARASITIC COLLECTOR-BASE CAPACITANCE 有权
标题翻译：具有降低的外延基底面积的双极接头晶体管对低的PARASIIC收集器电容的影响
公开(公告)号：US20140264341A1
公开(公告)日：2014-09-18
申请号：US13800091
申请日：2013-03-13
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Renata Camillo-Castillo , David L. Harame , Vibhor Jain , Vikas K. Kaushal , Marwan H. Khater
IPC分类号： H01L29/73 , H01L29/66
CPC分类号： H01L29/7371 , H01L21/7624 , H01L21/8249 , H01L29/04 , H01L29/0649 , H01L29/0817 , H01L29/0821 , H01L29/0826 , H01L29/1004 , H01L29/66242 , H01L29/66287 , H01L29/7325 , H01L2924/1305
摘要： Fabrication methods, device structures, and design structures for a bipolar junction transistor. A dielectric structure is formed that is coextensive with a single crystal semiconductor material of a substrate in an active device region. A semiconductor layer is formed that includes a single crystal section coupled with the active device region. The semiconductor layer has an edge that overlaps with a top surface of the dielectric structure. An intrinsic base layer is formed on the semiconductor layer.
摘要翻译：双极结晶体管的制造方法，器件结构和设计结构。形成与有源器件区域中的衬底的单晶半导体材料共同延伸的电介质结构。形成半导体层，其包括与有源器件区域耦合的单晶部分。半导体层具有与电介质结构的顶表面重叠的边缘。在半导体层上形成本征基层。

7. 发明申请

US20150137185A1 HETEROJUNCTION BIPOLAR TRANSISTORS WITH AN AIRGAP BETWEEN THE EXTRINSIC BASE AND COLLECTOR 有权
标题翻译：异位基体和收集器之间的空气间隔异构双极晶体管
公开(公告)号：US20150137185A1
公开(公告)日：2015-05-21
申请号：US14083769
申请日：2013-11-19
申请人： International Business Machines Corporation
发明人： Renata Camillo-Castillo , Vibhor Jain , Vikas K. Kaushal , Marwan H. Khater , Anthony K. Stamper
IPC分类号： H01L29/737 , H01L29/66
CPC分类号： H01L29/7371 , H01L29/0649 , H01L29/66242
摘要： Fabrication methods, device structures, and design structures for a heterojunction bipolar transistor. A collector is formed in a semiconductor substrate, an intrinsic base is formed on the semiconductor substrate, and an extrinsic base is formed on the intrinsic base. An airgap is located vertically between the extrinsic base and the collector. A contact surface is located adjacent to the airgap. The contact surface is coupled with the collector. A spacer is located laterally between the airgap and the subcollector contact surface.
摘要翻译：异质结双极晶体管的制造方法，器件结构和设计结构。在半导体衬底中形成集电极，在半导体衬底上形成本征基极，在本征基底上形成非本征基极。气隙垂直位于外部基极和收集器之间。接触表面位于气隙附近。接触表面与收集器结合。间隔件横向位于气隙和子集电极接触表面之间。

8. 发明授权

US09159817B2 Heterojunction bipolar transistors with an airgap between the extrinsic base and collector 有权
标题翻译：异质结双极晶体管，在外部基极和集电极之间具有气隙
公开(公告)号：US09159817B2
公开(公告)日：2015-10-13
申请号：US14083769
申请日：2013-11-19
申请人： International Business Machines Corporation
发明人： Renata Camillo-Castillo , Vibhor Jain , Vikas K. Kaushal , Marwan H. Khater , Anthony K. Stamper
IPC分类号： H01L29/66 , H01L29/73 , H01L29/737
CPC分类号： H01L29/7371 , H01L29/0649 , H01L29/66242
摘要： Fabrication methods, device structures, and design structures for a heterojunction bipolar transistor. A collector is formed in a semiconductor substrate, an intrinsic base is formed on the semiconductor substrate, and an extrinsic base is formed on the intrinsic base. An airgap is located vertically between the extrinsic base and the collector. A contact surface is located adjacent to the airgap. The contact surface is coupled with the collector. A spacer is located laterally between the airgap and the subcollector contact surface.
摘要翻译：异质结双极晶体管的制造方法，器件结构和设计结构。在半导体衬底中形成集电极，在半导体衬底上形成本征基极，在本征基底上形成非本征基极。气隙垂直位于外部基极和收集器之间。接触表面位于气隙附近。接触表面与收集器结合。间隔件横向位于气隙和子集电极接触表面之间。

9. 发明申请

US20140374802A1 BIPOLAR TRANSISTOR WITH MASKLESS SELF-ALIGNED EMITTER 有权
标题翻译：双极型晶体管，具有自由自对准发射极
公开(公告)号：US20140374802A1
公开(公告)日：2014-12-25
申请号：US13926644
申请日：2013-06-25
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： David L. Harame , Vikas K. Kaushal , Marwan H. Khater , Qizhi Liu
IPC分类号： H01L29/08 , H01L29/737 , H01L29/66
CPC分类号： H01L29/0817 , H01L29/0649 , H01L29/0804 , H01L29/41708 , H01L29/456 , H01L29/66242 , H01L29/66287 , H01L29/732 , H01L29/7378 , Y10S148/011
摘要： Embodiments of the present invention include a method for forming a semiconductor emitter and the resulting structure. The invention comprises forming an epitaxial base layer on a semiconductor substrate. A dielectric layer is deposited over the epitaxial base layer. An opening is etched in a portion of the dielectric layer exposing a portion of the epitaxial base layer and a spacer is deposited along the sidewall of the opening. The emitter is grown from the epitaxial base layer to overlap the top surface of the spacer and a portion of the dielectric layer. The single crystal emitter is formed without a mask and without the requirement of subsequent patterning processes.
摘要翻译：本发明的实施例包括形成半导体发射器的方法和所得到的结构。本发明包括在半导体衬底上形成外延基底层。介电层沉积在外延基底层上。在电介质层的暴露一部分外延基底层的部分中蚀刻开口，并且间隔物沿着开口的侧壁沉积。发射极从外延基底层生长以与间隔物的顶表面和电介质层的一部分重叠。单晶发射体不用掩模形成，不需要后续的图案化工艺。

10. 发明申请

US20140361300A1 BIPOLAR DEVICE HAVING A MONOCRYSTALLINE SEMICONDUCTOR INTRINSIC BASE TO EXTRINSIC BASE LINK-UP REGION 有权
标题翻译：具有单晶半导体内部基极到极端基底连接区的双极器件
公开(公告)号：US20140361300A1
公开(公告)日：2014-12-11
申请号：US13914707
申请日：2013-06-11
申请人： International Business Machines Corporation
发明人： Renata A. Camillo-Castillo , Vibhor Jain , Vikas K. Kaushal , Marwan H. Khater
IPC分类号： H01L29/10 , H01L29/66 , H01L29/737
CPC分类号： H01L29/1004 , H01L29/0653 , H01L29/66242 , H01L29/66272 , H01L29/732 , H01L29/7371
摘要： Disclosed are bipolar devices, which incorporate an entirely monocrystalline link-up region between the intrinsic and extrinsic base layers, and methods of forming the devices. In the methods, a selective epitaxial deposition process grows monocrystalline semiconductor material for the extrinsic base layer on an exposed edge portion of a monocrystalline section of an intrinsic base layer. This deposition process is continued to intentionally overgrow the monocrystalline semiconductor material until it grows laterally and essentially covers a dielectric landing pad on a center portion of that same monocrystalline section of the intrinsic base layer. Subsequently, an opening is formed through the extrinsic base layer to the dielectric landing pad and the dielectric landing pad is selectively removed, thereby exposing monocrystalline surfaces only of the intrinsic and extrinsic base layers. A semiconductor layer is then formed by epitaxial deposition on the exposed monocrystalline surfaces, thereby forming the entirely monocrystalline link-up region.
摘要翻译：公开了双极器件，其在内部和外部基极层之间并入完整的单晶连接区域，以及形成器件的方法。在该方法中，选择性外延沉积工艺在本征基底层的单晶部分的暴露边缘部分上生长外部基极层的单晶半导体材料。该沉积过程继续有意地过度生长单晶半导体材料，直到其横向生长并且基本上覆盖本征基层的相同单晶部分的中心部分上的电介质着陆焊盘。随后，通过外部基极层形成开口到电介质接合焊盘，并且选择性地去除电介质着陆焊盘，从而仅暴露出本征和外部基极层的单晶表面。然后通过外延沉积在暴露的单晶表面上形成半导体层，从而形成完全单晶连接区域。

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