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1. 发明申请

US20180287059A1 CROSSBAR RESISTIVE MEMORY ARRAY WITH HIGHLY CONDUCTIVE COPPER/COPPER ALLOY ELECTRODES AND SILVER/SILVER ALLOYS ELECTRODES 审中-公开
公开(公告)号：US20180287059A1
公开(公告)日：2018-10-04
申请号：US15473922
申请日：2017-03-30
申请人： International Business Machines Corporation
发明人： Takashi Ando , Marwan H. Khater , Seyoung Kim , Hiroyuki Miyazoe
IPC分类号： H01L45/00 , H01L27/24 , G06N3/04
CPC分类号： H01L45/1691 , G06N3/063 , H01L27/2463 , H01L45/085 , H01L45/1233 , H01L45/1253 , H01L45/146
摘要： Embodiments of the present invention provide systems and methods for the fabrication of a crossbar array fabrication of resistive random access memory (RRAM) cells. The array structure contains large grain copper and its alloy or silver and its alloy. A metal cap and spacer are used to protect copper or silver from chemical modifications during memory cell patterning.

2. 发明申请

US20180275344A1 SACRIFICIAL GRATING COUPLER FOR TESTING V-GROOVED INTEGRATED CIRCUITS 审中-公开
公开(公告)号：US20180275344A1
公开(公告)日：2018-09-27
申请号：US15992381
申请日：2018-05-30
申请人： International Business Machines Corporation
发明人： Tymon Barwicz , William M.J. Green , Jens Hofrichter , Marwan H. Khater , Jessie C. Rosenberg
IPC分类号： G02B6/136 , G02B6/30 , G02B6/34
CPC分类号： G02B6/136 , G02B6/305 , G02B6/34 , G02B6/423 , G02B2006/12061 , G02B2006/12107
摘要： Embodiments are directed to a method of forming an optical coupler system. The method includes forming at least one waveguide over a substrate, and forming a sacrificial optical coupler in a first region over the substrate. The method further includes configuring the sacrificial optical coupler to couple optical signals to or from the at least one waveguide, and forming a v-groove in the first region over the substrate, wherein forming the v-groove includes removing the sacrificial optical coupler from the first region.

3. 发明授权

US09887351B1 Multivalent oxide cap for analog switching resistive memory 有权
公开(公告)号：US09887351B1
公开(公告)日：2018-02-06
申请号：US15282202
申请日：2016-09-30
申请人： International Business Machines Corporation
发明人： Takashi Ando , Marwan H. Khater , Seyoung Kim , Hiroyuki Miyazoe
IPC分类号： H01L45/00 , H01L21/02
CPC分类号： H01L45/085 , H01L45/146 , H01L45/1608
摘要： A resistive random access memory (RRAM) includes a first electrode, a second electrode, a base oxide provided between the first electrode and the second electrode, and a multivalent oxide provided between the first electrode and the second electrode. The multivalent oxide switches between at least two oxidative states.

4. 发明授权

US09590001B2 CMOS protection during germanium photodetector processing 有权
标题翻译：锗光电探测器处理期间的CMOS保护
公开(公告)号：US09590001B2
公开(公告)日：2017-03-07
申请号：US14732835
申请日：2015-06-08
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Solomon Assefa , Marwan H. Khater , Edward W. Kiewra , Carol Reinholm , Steven M. Shank
IPC分类号： H01L27/146 , H01L27/144 , H01L31/028
CPC分类号： H01L27/14607 , H01L27/1443 , H01L27/14625 , H01L27/1463 , H01L27/14643 , H01L27/14689 , H01L31/028
摘要： A method of protecting a CMOS device within an integrated photonic semiconductor structure is provided. The method may include depositing a conformal layer of germanium over the CMOS device and an adjacent area to the CMOS device, depositing a conformal layer of dielectric hardmask over the germanium, and forming, using a mask level, a patterned layer of photoresist for covering the CMOS device and a photonic device formation region within the adjacent area. Openings are etched into areas of the deposited layer of silicon nitride not covered by the patterned photoresist, such that the areas are adjacent to the photonic device formation region. The germanium material is then etched from the conformal layer of germanium at a location underlying the etched openings for forming the photonic device at the photonic device formation region. The conformal layer of germanium deposited over the CMOS device protects the CMOS device.
摘要翻译：提供了保护集成光子半导体结构内的CMOS器件的方法。该方法可以包括在CMOS器件上沉积锗的保形层和与CMOS器件相邻的区域，在锗上沉积介电硬掩模的保形层，以及使用掩模级形成图案化的光致抗蚀剂层，以覆盖 CMOS器件和邻近区域内的光子器件形成区域。将开口蚀刻到未被图案化光致抗蚀剂覆盖的氮化硅的沉积层的区域中，使得该区域与光子器件形成区域相邻。然后在锗的共形层上蚀刻锗材料，其位于蚀刻开口下方的位置处，以在光子器件形成区域处形成光子器件。沉积在CMOS器件上的锗的保形层保护CMOS器件。

5. 发明授权

US09240448B2 Bipolar junction transistors with reduced base-collector junction capacitance 有权
标题翻译：具有降低的基极 - 集电极结电容的双极结晶体管
公开(公告)号：US09240448B2
公开(公告)日：2016-01-19
申请号：US14734713
申请日：2015-06-09
申请人： International Business Machines Corporation
发明人： James W. Adkisson , James R. Elliott , David L. Harame , Marwan H. Khater , Robert K. Leidy , Qizhi Liu , John J. Pekarik
IPC分类号： H01L29/732 , H01L29/06 , H01L29/10 , H01L29/08
CPC分类号： H01L29/0649 , H01L29/045 , H01L29/0804 , H01L29/0817 , H01L29/0821 , H01L29/1004 , H01L29/66242 , H01L29/66257 , H01L29/66287 , H01L29/73 , H01L29/7325 , H01L29/7375
摘要： Device structures for a bipolar junction transistor. The device structure includes a collector region, an intrinsic base formed on the collector region, an emitter coupled with the intrinsic base and separated from the collector by the intrinsic base, and an isolation region extending through the intrinsic base to the collector region. The isolation region is formed with a first section having first sidewalls that extend through the intrinsic base and a second section with second sidewalls that extend into the collector region. The second sidewalls are inclined relative to the first sidewalls. The isolation region is positioned in a trench that is formed with first and second etching process in which the latter etches different crystallographic directions of a single-crystal semiconductor material at different etch rates.
摘要翻译：双极结型晶体管的器件结构。器件结构包括集电极区域，形成在集电极区域上的本征基极，与本征基极耦合并与集电极与本征基极分离的发射极，以及延伸穿过本征基极到集电极区域的隔离区域。隔离区形成有具有延伸穿过本征基底的第一侧壁的第一部分和具有延伸到收集器区域中的第二侧壁的第二部分。第二侧壁相对于第一侧壁倾斜。隔离区域位于形成有第一和第二蚀刻工艺的沟槽中，其中后者以不同的蚀刻速率蚀刻单晶半导体材料的不同晶体方向。

6. 发明申请

US20150303229A1 CMOS PROTECTION DURING GERMANIUM PHOTODETECTOR PROCESSING 有权
公开(公告)号：US20150303229A1
公开(公告)日：2015-10-22
申请号：US14732835
申请日：2015-06-08
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Solomon Assefa , Marwan H. Khater , Edward W. Kiewra , Carol Reinholm , Steven M. Shank
IPC分类号： H01L27/146 , H01L31/028
CPC分类号： H01L27/14607 , H01L27/1443 , H01L27/14625 , H01L27/1463 , H01L27/14643 , H01L27/14689 , H01L31/028
摘要： A method of protecting a CMOS device within an integrated photonic semiconductor structure is provided. The method may include depositing a conformal layer of germanium over the CMOS device and an adjacent area to the CMOS device, depositing a conformal layer of dielectric hardmask over the germanium, and forming, using a mask level, a patterned layer of photoresist for covering the CMOS device and a photonic device formation region within the adjacent area. Openings are etched into areas of the deposited layer of silicon nitride not covered by the patterned photoresist, such that the areas are adjacent to the photonic device formation region. The germanium material is then etched from the conformal layer of germanium at a location underlying the etched openings for forming the photonic device at the photonic device formation region. The conformal layer of germanium deposited over the CMOS device protects the CMOS device.

7. 发明申请

US20150137185A1 HETEROJUNCTION BIPOLAR TRANSISTORS WITH AN AIRGAP BETWEEN THE EXTRINSIC BASE AND COLLECTOR 有权
标题翻译：异位基体和收集器之间的空气间隔异构双极晶体管
公开(公告)号：US20150137185A1
公开(公告)日：2015-05-21
申请号：US14083769
申请日：2013-11-19
申请人： International Business Machines Corporation
发明人： Renata Camillo-Castillo , Vibhor Jain , Vikas K. Kaushal , Marwan H. Khater , Anthony K. Stamper
IPC分类号： H01L29/737 , H01L29/66
CPC分类号： H01L29/7371 , H01L29/0649 , H01L29/66242
摘要： Fabrication methods, device structures, and design structures for a heterojunction bipolar transistor. A collector is formed in a semiconductor substrate, an intrinsic base is formed on the semiconductor substrate, and an extrinsic base is formed on the intrinsic base. An airgap is located vertically between the extrinsic base and the collector. A contact surface is located adjacent to the airgap. The contact surface is coupled with the collector. A spacer is located laterally between the airgap and the subcollector contact surface.
摘要翻译：异质结双极晶体管的制造方法，器件结构和设计结构。在半导体衬底中形成集电极，在半导体衬底上形成本征基极，在本征基底上形成非本征基极。气隙垂直位于外部基极和收集器之间。接触表面位于气隙附近。接触表面与收集器结合。间隔件横向位于气隙和子集电极接触表面之间。

8. 发明申请

US20140327111A1 TRENCH ISOLATION STRUCTURES AND METHODS FOR BIPOLAR JUNCTION TRANSISTORS 有权
标题翻译：用于双极晶体管的TRENCH隔离结构和方法
公开(公告)号：US20140327111A1
公开(公告)日：2014-11-06
申请号：US13874614
申请日：2013-05-01
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Renata Camillo-Castillo , Marwan H. Khater
IPC分类号： H01L29/06 , H01L29/732 , H01L29/66
CPC分类号： H01L29/0653 , H01L29/0649 , H01L29/66272 , H01L29/66287 , H01L29/732 , H01L29/7325 , H01L29/735 , H01L29/737
摘要： Device structures, fabrication methods, and design structures for a bipolar junction transistor. A first isolation region is formed in a substrate to define a lateral boundary for an active device region and an intrinsic base layer is formed on the substrate. The intrinsic base layer has a section overlying the active device region. After the intrinsic base layer is formed, the first isolation region is partially removed adjacent to the active device region to define a trench that is coextensive with the substrate in the active device region and that is coextensive with the first isolation region. The trench is at least partially filled with a dielectric material to define a second isolation region.
摘要翻译：双极结型晶体管的器件结构，制造方法和设计结构。第一隔离区域形成在衬底中以限定有源器件区域的横向边界，并且在衬底上形成本征基极层。本征基层具有覆盖有源器件区的部分。在本征基极层形成之后，第一隔离区域被部分地与有源器件区域相邻地去除，以限定与有源器件区域中的衬底共同延伸并且与第一隔离区域共同延伸的沟槽。沟槽至少部分地填充有电介质材料以限定第二隔离区域。

9. 发明申请

US20140217485A1 STRESS ENGINEERED MULTI-LAYERS FOR INTEGRATION OF CMOS AND Si NANOPHOTONICS 有权
公开(公告)号：US20140217485A1
公开(公告)日：2014-08-07
申请号：US14246546
申请日：2014-04-07
申请人： International Business Machines Corporation
发明人： Solomon Assefa , Tymon Barwicz , Swetha Kamlapurkar , Marwan H. Khater , Steven M. Shank , Yurii A. Vlasov
IPC分类号： H01L31/113
CPC分类号： H01L31/1136 , H01L27/1443
摘要： A method of forming an integrated photonic semiconductor structure having a photonic device and a CMOS device may include depositing a first silicon nitride layer having a first stress property over the photonic device, depositing an oxide layer having a stress property over the deposited first silicon nitride layer, and depositing a second silicon nitride layer having a second stress property over the oxide layer. The deposited first silicon nitride layer, the oxide layer, and the second silicon nitride layer encapsulate the photonic device.

10. 发明申请

US20140091374A1 STRESS ENGINEERED MULTI-LAYERS FOR INTEGRATION OF CMOS AND Si NANOPHOTONICS 有权
标题翻译：用于集成CMOS和Si纳米光子的应力工程多层
公开(公告)号：US20140091374A1
公开(公告)日：2014-04-03
申请号：US13629910
申请日：2012-09-28
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Solomon Assefa , Tymon Barwicz , Swetha Kamlapurkar , Marwan H. Khater , Steven M. Shank , Yurii A. Vlasov
IPC分类号： H01L27/14 , H01L31/18
CPC分类号： H01L31/1136 , H01L27/1443
摘要： A method of forming an integrated photonic semiconductor structure having a photonic device and a CMOS device may include depositing a first silicon nitride layer having a first stress property over the photonic device, depositing an oxide layer having a stress property over the deposited first silicon nitride layer, and depositing a second silicon nitride layer having a second stress property over the oxide layer. The deposited first silicon nitride layer, the oxide layer, and the second silicon nitride layer encapsulate the photonic device.
摘要翻译：形成具有光子器件和CMOS器件的集成光子半导体结构的方法可以包括在光子器件上沉积具有第一应力特性的第一氮化硅层，在沉积的第一氮化硅层上沉积具有应力特性的氧化物层并且在所述氧化物层上沉积具有第二应力特性的第二氮化硅层。沉积的第一氮化硅层，氧化物层和第二氮化硅层封装光子器件。

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