专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US10528865B2 System to duplicate neuromorphic core functionality 有权
公开(公告)号：US10528865B2
公开(公告)日：2020-01-07
申请号：US15188663
申请日：2016-06-21
申请人： International Business Machines Corporation
发明人： SangBum Kim , Chung H. Lam
IPC分类号： G06N3/063 , G11C13/00 , G06N3/04 , G06N3/08 , G11C11/54 , G11C7/10
摘要： A neuromorphic memory circuit including a memory cell with a programmable resistive memory element. A postsynaptic capacitor builds up a leaky integrate and fire (LIF) charge. An axon LIF pulse generator activates a LIF discharge path from the postsynaptic capacitor through the resistive memory element when the axon LIF pulse generator generates axon LIF pulses. A postsynaptic comparator compares the capacitor voltage to a threshold voltage and generates postsynaptic output pulses when the capacitor voltage passes the threshold voltage. The postsynaptic output pulses include a postsynaptic firing characteristic dependent on a frequency of the axon LIF pulses. A refractory circuit prevents the postsynaptic comparator from generating additional postsynaptic output pulses until a refractory time passes since a preceding postsynaptic output pulse. A training circuit adjusts the postsynaptic firing characteristic to match a target firing characteristic.

2. 发明申请

US20170222141A1 METAL NITRIDE KEYHOLE OR SPACER PHASE CHANGE MEMORY CELL STRUCTURES 审中-公开
公开(公告)号：US20170222141A1
公开(公告)日：2017-08-03
申请号：US15489368
申请日：2017-04-17
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Matthew Joseph BrightSky , SangBum Kim , Chung Hon Lam , Norma Edith Sosa
IPC分类号： H01L45/00
CPC分类号： H01L45/124 , H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/1253 , H01L45/143 , H01L45/144 , H01L45/1616 , H01L45/1683
摘要： Non-volatile memory cell having small programming power and a reduced resistance drift are provided. In one embodiment of the present application, a non-volatile memory cell is provided that includes a layer of dielectric material that has a via opening that exposes a surface of a bottom electrode. A metal nitride spacer is located along a bottom portion of each sidewall surface of the layer of dielectric material and in the via opening. A phase change material structure is present in the via opening and contacting a top portion of each sidewall surface of the layer of dielectric material and a topmost surface of each metal nitride spacer. A top electrode is located on a topmost surface of the phase change material structure.

3. 发明授权

US09627612B2 Metal nitride keyhole or spacer phase change memory cell structures 有权
公开(公告)号：US09627612B2
公开(公告)日：2017-04-18
申请号：US14633264
申请日：2015-02-27
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Matthew Joseph BrightSky , SangBum Kim , Chung Hon Lam , Norma Edith Sosa Cortes
IPC分类号： H01L45/00
CPC分类号： H01L45/124 , H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/1253 , H01L45/143 , H01L45/144 , H01L45/1616 , H01L45/1683
摘要： Non-volatile memory cell having small programming power and a reduced resistance drift are provided. In one embodiment of the present application, a non-volatile memory cell is provided that includes a layer of dielectric material that has a via opening that exposes a surface of a bottom electrode. A metal nitride spacer is located along a bottom portion of each sidewall surface of the layer of dielectric material and in the via opening. A phase change material structure is present in the via opening and contacting a top portion of each sidewall surface of the layer of dielectric material and a topmost surface of each metal nitride spacer. A top electrode is located on a topmost surface of the phase change material structure.

4. 发明申请

US20160203400A1 NEUROMORPHIC MEMORY CIRCUIT 有权
标题翻译：神经元存储器电路
公开(公告)号：US20160203400A1
公开(公告)日：2016-07-14
申请号：US14749413
申请日：2015-06-24
申请人： International Business Machines Corporation
发明人： SangBum Kim , Chung H. Lam
IPC分类号： G06N3/063
CPC分类号： G11C11/54 , G06N3/049 , G06N3/063 , G06N3/088 , G11C11/5678 , G11C13/0002 , G11C13/0004
摘要： A method for operating a neuromorphic memory circuit. The method includes accumulating a dendrite LIF charge over time on a conductive dendrite LIF line. A first transmitting operation transmits an axon LIF pulse on a conductive axon LIF line. A first switching operation switches on a LIF transistor by the axon LIF pulse such that the LIF transistor provides a discharge path for the dendrite LIF charge through a programmable resistive memory element when the axon LIF line transmits the axon LIF pulse. A second transmitting operation transmits a dendrite STDP pulse if the dendrite LIF charge falls below a threshold voltage. A third transmitting operation transmits an axon STDP pulse on a conductive axon STDP line. A second switching operation switches on a STDP transistor by the axon STDP pulse. The STDP transistor provides an electrical path for the dendrite STDP pulse through the programmable resistive memory element when the axon STDP line transmits the axon STDP pulse.
摘要翻译：一种用于操作神经形态记忆电路的方法。该方法包括在导电枝晶LIF线上随时间累积枝晶LIF电荷。第一次发送操作在导电轴突LIF线上发送轴突LIF脉冲。第一切换操作通过轴突LIF脉冲接通LIF晶体管，使得当轴突LIF线透射轴突LIF脉冲时，LIF晶体管通过可编程电阻存储器元件提供用于枝晶LIF电荷的放电路径。如果枝晶LIF电荷低于阈值电压，则第二次发送操作传输枝晶STDP脉冲。第三发送操作在导电轴突STDP线上发送轴突STDP脉冲。第二切换操作通过轴突STDP脉冲来接通STDP晶体管。当轴突STDP线传输轴突STDP脉冲时，STDP晶体管通过可编程电阻性存储器元件为枝晶STDP脉冲提供电路径。

5. 发明授权

US08953367B2 Three-dimensional memory array and operation scheme 有权
标题翻译：三维存储阵列和操作方案
公开(公告)号：US08953367B2
公开(公告)日：2015-02-10
申请号：US13958648
申请日：2013-08-05
申请人： International Business Machines Corporation
发明人： SangBum Kim , Chung H. Lam
IPC分类号： G11C11/00 , G11C13/00 , G11C11/21 , G11C7/18
CPC分类号： G11C13/0004 , G11C7/18 , G11C11/21 , G11C13/0007 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C2213/71 , G11C2213/78 , G11C2213/79 , H01L27/2454 , H01L27/249 , H01L45/04 , H01L45/06 , H01L45/1226
摘要： A system, method and computer program product for operating a three-dimensional memory array. An example array includes access transistors with first, second and gate terminals. Bit lines are coupled to the first terminals, word lines coupled to the gate terminals, and vertical lines are coupled to the second terminals. The bit, word, and vertical lines are perpendicular to one another. Memory cells are positioned along the vertical lines, including a bidirectional access device coupled in series with a memory element. The memory element is programmable to first and second states by application of first and second write voltages, opposite in polarity to one another. The array includes conductive plates parallel to the word and bit lines, and perpendicular to the vertical lines. The conductive plates are coupled to memory cells of the same height and separated by insulating layers.
摘要翻译：一种用于操作三维存储器阵列的系统，方法和计算机程序产品。示例性阵列包括具有第一，第二和栅极端子的存取晶体管。位线耦合到第一端子，耦合到栅极端子的字线和垂直线耦合到第二端子。位，字和垂直线彼此垂直。存储单元沿着垂直线定位，包括与存储元件串联耦合的双向访问设备。通过施加彼此极性相反的第一和第二写入电压，存储元件可编程为第一和第二状态。该阵列包括平行于字和位线并垂直于垂直线的导电板。导电板与相同高度的存储单元耦合，并由绝缘层隔开。

6. 发明申请

US20140160838A1 THREE-DIMENSIONAL MEMORY ARRAY AND OPERATION SCHEME 有权
公开(公告)号：US20140160838A1
公开(公告)日：2014-06-12
申请号：US13958648
申请日：2013-08-05
申请人： International Business Machines Corporation
发明人： SangBum Kim , Chung H. Lam
IPC分类号： G11C13/00
CPC分类号： G11C13/0004 , G11C7/18 , G11C11/21 , G11C13/0007 , G11C13/003 , G11C13/004 , G11C13/0069 , G11C2213/71 , G11C2213/78 , G11C2213/79 , H01L27/2454 , H01L27/249 , H01L45/04 , H01L45/06 , H01L45/1226
摘要： A system, method and computer program product for operating a three-dimensional memory array. An example array includes access transistors with first, second and gate terminals. Bit lines are coupled to the first terminals, word lines coupled to the gate terminals, and vertical lines are coupled to the second terminals. The bit, word, and vertical lines are perpendicular to one another. Memory cells are positioned along the vertical lines, including a bidirectional access device coupled in series with a memory element. The memory element is programmable to first and second states by application of first and second write voltages, opposite in polarity to one another. The array includes conductive plates parallel to the word and bit lines, and perpendicular to the vertical lines. The conductive plates are coupled to memory cells of the same height and separated by insulating layers.

7. 发明申请

US20200082256A1 NEURON PERIPHERAL CIRCUITS FOR NEUROMORPHIC SYNAPTIC MEMORY ARRAY BASED ON NEURON MODELS 审中-公开
公开(公告)号：US20200082256A1
公开(公告)日：2020-03-12
申请号：US16680506
申请日：2019-11-12
申请人： International Business Machines Corporation
发明人： Kohji Hosokawa , Masatoshi Ishii , SangBum Kim , Chung H. Lam , Scott C. Lewis
IPC分类号： G06N3/063 , G06N3/04
摘要： A neuromorphic memory system including neuromorphic memory arrays. The neuromorphic memory system includes a presynaptic neuron circuit coupled to a postsynaptic neuron circuit by a resistive memory cell. The method includes generating a presynaptic LIF pulse on a presynaptic LIF line at time t1. An activating operation activates an access transistor coupled to the presynaptic LIF line in response to the presynaptic LIF pulse. The access transistor enables LIF current to pass through the resistive memory cell to a postsynaptic LIF line. An integrating operation integrates the LIF current at the postsynaptic LIF line over time. A comparing operation compares a LIF voltage at the postsynaptic LIF line to a threshold voltage. A generating operation generates a postsynaptic spike timing dependent plasticity (STDP) pulse on a postsynaptic STDP line if the LIF voltage is beyond the threshold voltage.

8. 发明授权

US10572799B2 Neuron peripheral circuits for neuromorphic synaptic memory array based on neuron models 有权
公开(公告)号：US10572799B2
公开(公告)日：2020-02-25
申请号：US14749331
申请日：2015-06-24
申请人： International Business Machines Corporation
发明人： Kohji Hosokawa , Masatoshi Ishii , SangBum Kim , Chung H. Lam , Scott C. Lewis
IPC分类号： G06N3/063 , G06N3/04
摘要： A neuromorphic memory system including neuromorphic memory arrays. The neuromorphic memory system includes a presynaptic neuron circuit coupled to a postsynaptic neuron circuit by a resistive memory cell. The method includes generating a presynaptic LIF pulse on a presynaptic LIF line at time t1. An activating operation activates an access transistor coupled to the presynaptic LIF line in response to the presynaptic LIF pulse. The access transistor enables LIF current to pass through the resistive memory cell to a postsynaptic LIF line. An integrating operation integrates the LIF current at the postsynaptic LIF line over time. A comparing operation compares a LIF voltage at the postsynaptic LIF line to a threshold voltage. A generating operation generates a postsynaptic spike timing dependent plasticity (STDP) pulse on a postsynaptic STDP line if the LIF voltage is beyond the threshold voltage.

9. 发明授权

US10169701B2 Neuron peripheral circuits for neuromorphic synaptic memory array based on neuron models 有权
公开(公告)号：US10169701B2
公开(公告)日：2019-01-01
申请号：US14722008
申请日：2015-05-26
申请人： International Business Machines Corporation
发明人： Kohji Hosokawa , Masatoshi Ishii , SangBum Kim , Chung H. Lam , Scott C. Lewis
IPC分类号： G06N3/063 , G06N3/04
摘要： A neuromorphic memory system including neuromorphic memory arrays. Each neuromorphic memory array includes rows and columns of neuromorphic memory cells. A column of postsynaptic circuits is electrically coupled to postsynaptic spike timing dependent plasticity (STDP) lines. Each postsynaptic STDP line is coupled to a row of neuromorphic memory cells. A column of summing circuits is electrically coupled to postsynaptic leaky integrate and fire (LIF) lines. Each postsynaptic LIF line is coupled to the row of neuromorphic memory cells at a respective memory array. Each summing circuit provides a sum of signals from the postsynaptic LIF lines to a respective postsynaptic circuit.

10. 发明授权

US09830982B2 Neuromorphic memory circuit using a dendrite leaky integrate and fire (LIF) charge 有权
公开(公告)号：US09830982B2
公开(公告)日：2017-11-28
申请号：US14749413
申请日：2015-06-24
申请人： International Business Machines Corporation
发明人： SangBum Kim , Chung H. Lam
IPC分类号： G06F15/18 , G11C11/54 , G06N3/063 , G11C11/56 , G11C13/00 , G06N3/04 , G06N3/08
CPC分类号： G11C11/54 , G06N3/049 , G06N3/063 , G06N3/088 , G11C11/5678 , G11C13/0002 , G11C13/0004
摘要： A method for operating a neuromorphic memory circuit. The method includes accumulating a dendrite LIF charge over time on a conductive dendrite LIF line. A first transmitting operation transmits an axon LIF pulse on a conductive axon LIF line. A first switching operation switches on a LIF transistor by the axon LIF pulse such that the LIF transistor provides a discharge path for the dendrite LIF charge through a programmable resistive memory element when the axon LIF line transmits the axon LIF pulse. A second transmitting operation transmits a dendrite STDP pulse if the dendrite LIF charge falls below a threshold voltage. A third transmitting operation transmits an axon STDP pulse on a conductive axon STDP line. A second switching operation switches on a STDP transistor by the axon STDP pulse. The STDP transistor provides an electrical path for the dendrite STDP pulse through the programmable resistive memory element when the axon STDP line transmits the axon STDP pulse.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式