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1. 发明申请

US20040210802A1 REDUNDANCY REGISTER ARCHITECTURE FOR SOFT-ERROR TOLERANCE AND METHODS OF MAKING THE SAME 失效
标题翻译：用于软错误容忍的冗余注册架构及其制作方法
公开(公告)号：US20040210802A1
公开(公告)日：2004-10-21
申请号：US10249574
申请日：2003-04-21
申请人： International Business Machines Corporation
发明人： Jeffery H. Oppold , Michael R. Ouellette , Larry Wissel
IPC分类号： G11C029/00
CPC分类号： G11C5/005 , G11C11/4125 , G11C29/787
摘要： A redundancy register architecture associated with a RAM provides for soft-error tolerance. An enable register provides soft error rate protection to the registers that contain replacement information for redundant rows and columns. The gate register determines whether a row or column replacement register contains a specific address, and parity protection to the replacement register is activated as necessitated. The register architecture is changed to make the register state a nulldon't carenull state for the majority of the registers. A small number of registers that are critical to the redundancy system are identified and made more robust to upsets. Word-line and column-line substitution is implemented. A ripple parity scheme is implemented when parity checks are activated.
摘要翻译：与RAM相关联的冗余寄存器架构提供了软错误容限。启用寄存器为包含冗余行和列的替换信息的寄存器提供软错误率保护。门寄存器确定行或列替换寄存器是否包含特定地址，并且根据需要激活替换寄存器的奇偶校验保护。更改寄存器架构，使寄存器状态成为大多数寄存器的“无关”状态。识别对冗余系统至关重要的少量寄存器，并使其变得更加鲁棒。实现字线和列行替代。当奇偶校验被激活时，实现纹波奇偶校验方案。

2. 发明申请

US20040251475A1 Zero threshold voltage pFET and method of making same 失效
标题翻译：零阈值电压pFET及其制作方法
公开(公告)号：US20040251475A1
公开(公告)日：2004-12-16
申请号：US10845835
申请日：2004-05-14
申请人： International Business Machines Corporation
发明人： Jeffrey S. Brown , Chung H. Lam , Randy W. Mann , Jeffery H. Oppold
IPC分类号： H01L029/76
CPC分类号： H01L29/1037 , H01L21/823412 , H01L21/823493 , H01L29/78
摘要： A zero threshold voltage (ZVt) pFET (104) and a method of making the same. The ZVt pFET is made by implanting a p-type substrate (112) with a retrograde n-well (116) so that a pocket (136) of the p-type substrate material remains adjacent the surface of the substrate. This is accomplished using an n-well mask (168) having a pocket-masking region (184) in the aperture (180) corresponding to the ZVt pFET. The n-well may be formed by first creating a ring-shaped precursor n-well (116null) and then annealing the substrate so as to cause the regions of the lower portion (140null) of the precursor n-well to merge with one another to isolate the pocket of p-type substrate material. After the n-well and isolated pocket of p-type substrate material have been formed, remaining structures of the ZVt pFET may be formed, such as a gate insulator (128), gate (132), source (120), and drain (124).
摘要翻译：零阈值电压（ZVt）pFET（104）及其制造方法。 ZVt pFET通过用逆向n阱（116）注入p型衬底（112），使得p型衬底材料的凹口（136）保持邻近衬底的表面而制成。这是通过在对应于ZVt pFET的孔径（180）中具有口罩掩蔽区域（184）的n阱掩模（168）来实现的。可以通过首先产生环形前体n阱（116'）然后对衬底退火以使前体n阱的下部（140'）的区域与彼此隔开p型衬底材料的口袋。在已经形成p型衬底材料的n阱和隔离袋之后，可以形成ZVt pFET的剩余结构，例如栅极绝缘体（128），栅极（132），源极（120）和漏极（ 124）。

3. 发明申请

US20040001376A1 Method and design for measuring SRAM array leakage macro (ALM) 失效
公开(公告)号：US20040001376A1
公开(公告)日：2004-01-01
申请号：US10064302
申请日：2002-07-01
申请人： International Business Machines Corporation
发明人： Matthew J. Breitwisch , Jeffrey S. Brown , Randy W. Mann , Jeffery H. Oppold
IPC分类号： G11C029/00
CPC分类号： G11C29/50 , G11C11/41 , G11C2029/5006
摘要： A method and structure for a test structure that has an array of cells connected together by conductive lines. The conductive lines connect the cells together as if they were a single cell. The conductive lines can include common word line; a common bit line; a common bit line complement line, a common N-well voltage line, a common interior ground line, a common interior voltage line, and/or a common ground line.

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