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1. 发明授权

US09870960B2 Capacitance monitoring using X-ray diffraction 有权
$Capacitance monitoring using X-ray diffraction$
公开(公告)号：US09870960B2
公开(公告)日：2018-01-16
申请号：US14575134
申请日：2014-12-18
申请人： International Business Machines Corporation
发明人： Donghun Kang , Kriteshwar K. Kohli , Oh-jung Kwon , Anita Madan , Conal E. Murray
IPC分类号： H01L21/00 , H01L21/66 , G01N23/20 , G01R31/265
CPC分类号： H01L22/14 , G01N23/20 , G01N23/207 , G01N2223/0566 , G01N2223/607 , G01N2223/611 , G01R31/2656 , H01L22/12
摘要： A method includes measuring a difference between a primary X-ray diffraction peak and a secondary X-ray diffraction peak, the primary X-ray diffraction peak corresponds to an unstrained portion of a semiconductor substrate and the secondary X-ray diffraction peak corresponds to a strained portion of the semiconductor substrate, the difference between the primary X-ray diffraction peak and the secondary X-ray diffraction peak includes a delta shift peak that corresponds to changes in a crystal lattice caused by a stress applied to the strained portion of the semiconductor substrate, the delta shift peak includes variations in a deep trench capacitance.

2. 发明授权

US09087927B2 Thermally stable high-K tetragonal HFO2 layer within high aspect ratio deep trenches 有权
标题翻译：高稳定性高K四方HFO2层在高深宽比深沟内
公开(公告)号：US09087927B2
公开(公告)日：2015-07-21
申请号：US14521743
申请日：2014-10-23
申请人： International Business Machines Corporation
发明人： Michael P. Chudzik , Bachir Dirahoui , Rishikesh Krishnan , Siddarth A. Krishnan , Oh-jung Kwon , Paul C. Parries , Hongwen Yan
IPC分类号： H01L49/02 , H01L21/84 , H01L27/108 , H01L29/94 , H01L27/12 , H01L21/02
CPC分类号： H01L28/91 , H01L21/02181 , H01L21/0228 , H01L21/02321 , H01L21/84 , H01L27/10847 , H01L27/1087 , H01L27/1203 , H01L29/945
摘要： A trench structure that in one embodiment includes a trench present in a substrate, and a dielectric layer that is continuously present on the sidewalls and base of the trench. The dielectric layer has a dielectric constant that is greater than 30. The dielectric layer is composed of tetragonal phase hafnium oxide with silicon present in the grain boundaries of the tetragonal phase hafnium oxide in an amount ranging from 3 wt. % to 20 wt. %.
摘要翻译：在一个实施例中的沟槽结构包括存在于衬底中的沟槽，以及连续存在于沟槽的侧壁和基底上的电介质层。电介质层的介电常数大于30.介电层由四方相铪氧化物组成，其中硅存在于四方相铪氧化物的晶界中，其量为3wt。％至20重量％％。

3. 发明申请

US20150044853A1 THERMALLY STABLE HIGH-K TETRAGONAL HFO2 LAYER WITHIN HIGH ASPECT RATIO DEEP TRENCHES 有权
标题翻译：高稳定度高深度条件下的热稳定性高K TETRAGONAL HFO2层
公开(公告)号：US20150044853A1
公开(公告)日：2015-02-12
申请号：US14521743
申请日：2014-10-23
申请人： International Business Machines Corporation
发明人： Michael P. Chudzik , Bachir Dirahoui , Rishikesh Krishnan , Siddarth A. Krishnan , Oh-jung Kwon , Paul C. Parries , Hongwen Yan
IPC分类号： H01L49/02 , H01L27/108
CPC分类号： H01L28/91 , H01L21/02181 , H01L21/0228 , H01L21/02321 , H01L21/84 , H01L27/10847 , H01L27/1087 , H01L27/1203 , H01L29/945
摘要： A trench structure that in one embodiment includes a trench present in a substrate, and a dielectric layer that is continuously present on the sidewalls and base of the trench. The dielectric layer has a dielectric constant that is greater than 30. The dielectric layer is composed of tetragonal phase hafnium oxide with silicon present in the grain boundaries of the tetragonal phase hafnium oxide in an amount ranging from 3 wt. % to 20 wt. %.
摘要翻译：在一个实施例中的沟槽结构包括存在于衬底中的沟槽，以及连续存在于沟槽的侧壁和基底上的电介质层。电介质层的介电常数大于30.介电层由四方相铪氧化物组成，其中硅存在于四方相铪氧化物的晶界中，其量为3wt。％至20重量％％。

4. 发明申请

US20180096904A1 CAPACITANCE MONITORING USING X-RAY DIFFRACTION 有权
公开(公告)号：US20180096904A1
公开(公告)日：2018-04-05
申请号：US15831810
申请日：2017-12-05
申请人： International Business Machines Corporation
发明人： Donghun Kang , Kriteshwar K. Kohli , Oh-jung Kwon , Anita Madan , Conal E. Murray
IPC分类号： H01L21/66 , G01N23/20 , G01R31/265
CPC分类号： H01L22/14 , G01N23/20 , G01N23/207 , G01N2223/0566 , G01N2223/607 , G01N2223/611 , G01R31/2656 , H01L22/12
摘要： A method includes measuring a difference between a primary X-ray diffraction peak and a secondary X-ray diffraction peak, the primary X-ray diffraction peak corresponds to an unstrained portion of a semiconductor substrate and the secondary X-ray diffraction peak corresponds to a strained portion of the semiconductor substrate, the difference between the primary X-ray diffraction peak and the secondary X-ray diffraction peak includes a delta shift peak that corresponds to changes in a crystal lattice caused by a stress applied to the strained portion of the semiconductor substrate, the delta shift peak includes variations in a deep trench capacitance.

5. 发明授权

US09240452B2 Array and moat isolation structures and method of manufacture 有权
标题翻译：阵列和护城隔离结构及其制造方法
公开(公告)号：US09240452B2
公开(公告)日：2016-01-19
申请号：US14149280
申请日：2014-01-07
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Naoyoshi Kusaba , Oh-jung Kwon , Zhengwen Li , Hongwen Yan
IPC分类号： H01L29/06 , H01L29/423 , H01L27/108 , H01L29/66 , H01L29/94 , H01L21/762
CPC分类号： H01L29/423 , H01L21/762 , H01L27/10805 , H01L27/10829 , H01L27/1087 , H01L29/66181 , H01L29/945
摘要： An array or moat isolation structure for eDRAM with heterogeneous deep trench fill and methods of manufacture is provided. The method includes forming a deep trench for a memory array and an isolation region. The method further includes forming a node dielectric on exposed surfaces of the deep trench for the memory array and the isolation region. The method further includes filling remaining portions of the deep trench for the memory array with a metal, and lining the deep trench of the isolation region with the metal. The method further includes filling remaining portions of the deep trench for the isolation region with a material, on the metal within the deep trench for the memory array. The method further includes recessing the metal within the deep trench for the memory array and the isolation region. The metal in the deep trench of the memory array is recessed to a greater depth than the metal in the isolation region.
摘要翻译：提供了具有异质深沟槽填充的eDRAM的阵列或护城河隔离结构和制造方法。该方法包括形成用于存储器阵列的深沟槽和隔离区域。该方法还包括在用于存储器阵列和隔离区域的深沟槽的暴露表面上形成节点电介质。该方法还包括用金属填充用于存储器阵列的深沟槽的剩余部分，并且用金属衬里隔离区域的深沟槽。该方法还包括用用于存储器阵列的深沟槽内的金属上的材料填充用于隔离区的深沟槽的剩余部分。该方法还包括使用于存储器阵列和隔离区域的深沟槽内的金属凹陷。存储器阵列的深沟槽中的金属凹陷到比隔离区域中的金属更深的深度。

6. 发明申请

US20150364362A1 WAFER STRESS CONTROL WITH BACKSIDE PATTERNING 有权
标题翻译：具有背面图案的波浪压力控制
公开(公告)号：US20150364362A1
公开(公告)日：2015-12-17
申请号：US14306598
申请日：2014-06-17
申请人： International Business Machines Corporation
发明人： Edward Engbrecht , Donghun Kang , Rishikesh Krishnan , Oh-jung Kwon , Karen A. Nummy
IPC分类号： H01L21/762 , H01L21/66 , H01L29/06 , H01L21/308 , H01L21/321
CPC分类号： H01L21/76227 , H01L21/302 , H01L21/308 , H01L21/3081 , H01L21/3212 , H01L22/12 , H01L29/0603 , H01L29/945
摘要： Embodiments of the present invention provide structures and methods for controlling stress in semiconductor wafers during fabrication. Features such as deep trenches (DTs) used in circuit elements such as trench capacitors impart stress on a wafer that is proportional to the surface area of the DTs. In embodiments, a corresponding pattern of dummy (non-functional) DTs is formed on the back side of the wafer to counteract the electrically functional DTs formed on the front side of a wafer. In some embodiments, the corresponding pattern on the back side is a mirror pattern that matches the functional (front side) pattern in size, placement, and number. By creating the minor pattern on both sides of the wafer, the stresses on the front and back of the wafer are in balance. This helps reduce topography issues such as warping that can cause problems during wafer fabrication.
摘要翻译：本发明的实施例提供了在制造期间控制半导体晶片中的应力的结构和方法。诸如沟槽电容器的电路元件中使用的诸如深沟槽（DT）的特征赋予与DT的表面积成比例的晶片上的应力。在实施例中，虚拟（非功能）DT的相应图案形成在晶片的背面，以抵消形成在晶片正面上的电功能DT。在一些实施例中，背面上的对应图案是与尺寸，布局和数量上的功能（前侧）图案相匹配的镜面图案。通过在晶片的两侧形成次要图案，晶片正面和背面的应力平衡。这有助于减少在晶圆制造过程中可能导致问题的翘曲等形貌问题。

7. 发明授权

US10008421B2 Capacitance monitoring using x-ray diffraction 有权
$Capacitance monitoring using x-ray diffraction$
公开(公告)号：US10008421B2
公开(公告)日：2018-06-26
申请号：US15831810
申请日：2017-12-05
申请人： International Business Machines Corporation
发明人： Donghun Kang , Kriteshwar K. Kohli , Oh-jung Kwon , Anita Madan , Conal E. Murray
IPC分类号： H01L21/00 , H01L21/66 , G01R31/265 , G01N23/20
CPC分类号： H01L22/14 , G01N23/20 , G01N23/207 , G01N2223/0566 , G01N2223/607 , G01N2223/611 , G01R31/2656 , H01L22/12
摘要： A method includes measuring a difference between a primary X-ray diffraction peak and a secondary X-ray diffraction peak, the primary X-ray diffraction peak corresponds to an unstrained portion of a semiconductor substrate and the secondary X-ray diffraction peak corresponds to a strained portion of the semiconductor substrate, the difference between the primary X-ray diffraction peak and the secondary X-ray diffraction peak includes a delta shift peak that corresponds to changes in a crystal lattice caused by a stress applied to the strained portion of the semiconductor substrate, the delta shift peak includes variations in a deep trench capacitance.

8. 发明申请

US20160178679A1 CAPACITANCE MONITORING USING X-RAY DIFFRACTION 有权
标题翻译：使用X射线衍射进行电容监测
公开(公告)号：US20160178679A1
公开(公告)日：2016-06-23
申请号：US14575134
申请日：2014-12-18
申请人： International Business Machines Corporation
发明人： Donghun Kang , Kriteshwar K. Kohli , Oh-jung Kwon , Anita Madan , Conal E. Murray
IPC分类号： G01R27/26 , G01R31/265 , H01L21/66 , G01N23/20
CPC分类号： H01L22/14 , G01N23/20 , G01N23/207 , G01N2223/0566 , G01N2223/607 , G01N2223/611 , G01R31/2656 , H01L22/12
摘要： A method includes measuring a difference between a primary X-ray diffraction peak and a secondary X-ray diffraction peak, the primary X-ray diffraction peak corresponds to an unstrained portion of a semiconductor substrate and the secondary X-ray diffraction peak corresponds to a strained portion of the semiconductor substrate, the difference between the primary X-ray diffraction peak and the secondary X-ray diffraction peak includes a delta shift peak that corresponds to changes in a crystal lattice caused by a stress applied to the strained portion of the semiconductor substrate, the delta shift peak includes variations in a deep trench capacitance.
摘要翻译：一种方法包括测量主X射线衍射峰和次X射线衍射峰之间的差异，主X射线衍射峰对应于半导体衬底的未应变部分，并且次X射线衍射峰对应于半导体衬底的应变部分，初级X射线衍射峰和次级X射线衍射峰之间的差包括对应于施加到半导体的应变部分的应力引起的晶格变化的δ偏移峰衬底，δ偏移峰包括深沟槽电容的变化。

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