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1. 发明申请

US20040063277A1 Semiconductor method and structure for simultaneously forming a trench capacitor dielectric and trench sidewall device dielectric 失效
标题翻译：用于同时形成沟槽电容器电介质和沟槽侧壁器件电介质的半导体方法和结构
公开(公告)号：US20040063277A1
公开(公告)日：2004-04-01
申请号：US10260085
申请日：2002-09-27
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Michael P. Chudzik , Rajarao Jammy , Carl John Radens , Kenneth T. Settlemyer JR. , Padraic Shafer , Joseph F. Shepard JR.
IPC分类号： H01L021/8242
CPC分类号： H01L29/66181 , H01L21/3144 , H01L21/31616 , H01L21/31641 , H01L21/31645 , H01L21/31691 , H01L27/10864 , H01L27/10867
摘要： Disclosed herein is a method, in an integrated, of forming a high-K node dielectric of a trench capacitor and a trench sidewall device dielectric at the same time. The method includes forming a trench in a single crystal layer of a semiconductor substrate, and forming an isolation collar along a portion of the trench sidewall, wherein the collar has a top below the top of the trench in the single crystal layer. Then, at the same time, a high-K dielectric is formed along the trench sidewall, the high-K dielectric extending in both an upper portion of the trench including above the isolation collar and in a lower portion of the trench below the isolation collar. The top of the isolation collar is then etched back to expose a portion of the single crystal substrate along the sidewall, and then, a node electrode is formed in conductive contact with the exposed sidewall and also in contact with the high-K dielectric in the lower portion, such that the high-K dielectric remains as a trench sidewall dielectric in the upper portion of the sidewall. In a DRAM memory cell structure, the trench sidewall dielectric may then be used as a gate dielectric of a vertical transistor which accesses the trench storage capacitor in the trench.
摘要翻译：本文公开了一种在同时形成沟槽电容器和沟槽侧壁装置电介质的高K节点电介质的集成方法。所述方法包括在半导体衬底的单晶层中形成沟槽，以及沿着沟槽侧壁的一部分形成隔离环，其中所述环在所述单晶层中具有位于所述沟槽顶部下方的顶部。然后，同时，沿着沟槽侧壁形成高K电介质，高K电介质在包括隔离环的上方的沟槽的上部和隔离环的下方的沟槽的下部延伸。然后隔离环的顶部被回蚀以沿着侧壁露出单晶衬底的一部分，然后，形成与暴露的侧壁导电接触并且还与高K电介质接触的节点电极使得高K电介质保留在侧壁的上部中的沟槽侧壁电介质。在DRAM存储单元结构中，沟槽侧壁电介质可以用作访问沟槽中的沟槽存储电容器的垂直晶体管的栅极电介质。

2. 发明申请

US20030207532A1 METHOD AND STRUCTURE FOR SALICIDE TRENCH CAPACITOR PLATE ELECTRODE 失效
标题翻译：硫酸盐电容电极板电极的方法与结构
公开(公告)号：US20030207532A1
公开(公告)日：2003-11-06
申请号：US10137268
申请日：2002-05-01
申请人： International Business Machines Corporation
发明人： Michael Patrick Chudzik , Jack Allan Mandelman , Carl John Radens , Rajarao Jammy , Kenneth T. Settlemyer JR. , Padraic C. Shafer , Joseph F. Shepard JR.
IPC分类号： H01L021/8242
CPC分类号： H01L29/66181 , H01L27/10829 , H01L27/10861 , H01L27/1087 , H01L29/945
摘要： The present invention is a method and structure for fabricating a trench capacitor within a semiconductor substrate having a buried plate electrode formed of metal silicide. A collar is formed in a trench etched into a substrate; a conformal metal film is deposited thereover, and is annealed to form a silicide that is self-aligned to the collar. Silicide will not be formed on the collar, pads and other areas where the silicon is not directly exposed and hence the metal layer can be removed from these areas by selective etching.
摘要翻译：本发明是一种在具有由金属硅化物形成的掩埋板电极的半导体衬底内制造沟槽电容器的方法和结构。在蚀刻到衬底中的沟槽中形成凸缘; 在其上沉积保形金属膜，并对其进行退火以形成与套环自对准的硅化物。硅胶不会形成在硅胶不直接暴露的环，垫和其它区域，因此金属层可以通过选择性蚀刻从这些区域中去除。

3. 发明申请

US20040036100A1 STRUCTURE AND METHOD OF FABRICATING EMBEDDED DRAM HAVING A VERTICAL DEVICE ARRAY AND A BORDERED BITLINE CONTACT 有权
标题翻译：具有垂直设备阵列和边界位线接触的嵌入式DRAM的结构和方法
公开(公告)号：US20040036100A1
公开(公告)日：2004-02-26
申请号：US10227404
申请日：2002-08-23
申请人： International Business Machines Corporation
发明人： Ramachandra Divakaruni , Babar Ali Khan , Carl John Radens
IPC分类号： H01L021/8242
CPC分类号： H01L27/10891 , H01L27/0207 , H01L27/10864
摘要： An integrated circuit including a dynamic random access memory (DRAM) array is disclosed herein in which a DRAM cell includes a storage capacitor within a deep trench, a transistor having a channel extending along a sidewall of the deep trench and a gate conductor within the deep trench, and a wordline contacting the gate conductor from above, wherein the wordline has a centerline which is offset from the centerline of the gate conductor. The DRAM cell-further includes active area extending from the transistor channel, and a bitline contact to the active area which is bordered by an insulating spacer of the sidewall of the wordline.
摘要翻译：本文公开了一种包括动态随机存取存储器（DRAM）阵列的集成电路，其中DRAM单元在深沟槽内包括存储电容器，具有沿着深沟槽的侧壁延伸的沟道的晶体管和深沟槽内的栅极导体沟槽和从上方接触栅极导体的字线，其中字线具有偏离栅极导体的中心线的中心线。 DRAM单元还包括从晶体管沟道延伸的有源区，以及与由字线的侧壁的绝缘间隔物界定的有源区的位线接触。

4. 发明申请

US20040066666A1 Structure and method of vertical transistor DRAM cell having a low leakage buried strap 失效
标题翻译：具有低泄漏掩埋带的垂直晶体管DRAM单元的结构和方法
公开(公告)号：US20040066666A1
公开(公告)日：2004-04-08
申请号：US10265558
申请日：2002-10-04
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Dureseti Chidambarrao , Jack Allan Mandelman , Carl John Radens
IPC分类号： G11C011/24
CPC分类号： H01L27/10867 , H01L27/10864
摘要： A structure and method is disclosed herein for a vertical transistor DRAM cell having a low leakage buried strap outdiffusion conductively connecting a storage capacitor in a lower portion of a trench to a vertical transistor thereabove. In the disclosed structure and method, the buried strap outdiffusion (BSOD) extends along a portion of the isolation collar having reduced thickness, the reduced thickness being substantially less than the thickness of the isolation collar otherwise. In a particular embodiment, a self-aligned lightly doped drain (LDD) extension is formed, extending between the BSOD and the vertical transistor above the LDD.
摘要翻译：本文公开了一种用于垂直晶体管DRAM单元的结构和方法，该垂直晶体管DRAM单元具有将沟槽下部的存储电容器导电连接到其上方的垂直晶体管的低泄漏掩埋带外扩散。在所公开的结构和方法中，掩埋带外扩散（BSOD）沿着具有减小的厚度的隔离环的一部分延伸，否则减小的厚度小于隔离环的厚度。在特定实施例中，形成自对准的轻掺杂漏极（LDD）延伸，在LDD之上的BSOD和垂直晶体管之间延伸。

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