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1. 发明申请

US20040104420A1 PREVENTION OF Ta2O5 MIM CAP SHORTING IN THE BEOL ANNEAL CYCLES 有权
标题翻译：防止Ta2O5 MIM帽在BEOL中的周期循环
公开(公告)号：US20040104420A1
公开(公告)日：2004-06-03
申请号：US10249550
申请日：2003-04-17
申请人： International Business Machines Corporation
发明人： Douglas D. Coolbaugh , Ebenezer E. Eshun , Joseph F. Shepard JR. , Kenneth J. Stein , Kunal Vaed
IPC分类号： H01L029/76
CPC分类号： H01L28/40 , H01L21/31604 , H01L28/55
摘要： The present invention provides a high-performance metal-insulator-metal (MIM) capacitor which contains a high-k dielectric, yet no substantial shorting of the MIM capacitor is observed. Specifically, shorting of the MIM capacitor is substantially prevented in the present invention by forming a passivation layer between the high-k dielectric layer and each of the capacitornulls electrodes. The inventive MIM capacitor includes a first conductor; a first passivation layer located atop the first conductor; a high-k dielectric layer located atop the first passivation layer; a second passivation layer located atop the high k dielectric layer; and a second conductor located atop the second passivation layer.
摘要翻译：本发明提供了一种高性能金属绝缘体金属（MIM）电容器，其包含高k电介质，但没有观察到MIM电容器的实质短路。具体地说，在本发明中通过在高k电介质层和电容器电极之间形成钝化层，实质上防止了MIM电容器的短路，本发明的MIM电容器包括：第一导体;位于顶部的第一钝化层所述第一导体;位于所述第一钝化层顶部的高k电介质层;位于所述高k电介质层顶部的第二钝化层;以及位于所述第二钝化层顶部的第二导体。

2. 发明申请

US20020106857A1 Method for surface area enhancement of capacitors by film growth and self masking 审中-公开
标题翻译：通过膜生长和自我掩蔽的电容器表面积增强的方法
公开(公告)号：US20020106857A1
公开(公告)日：2002-08-08
申请号：US09777445
申请日：2001-02-06
申请人： International Business Machines Corporation
发明人： Rajarao Jammy , Irene McStay , Byeongju Park , Ravikumar Ramachandran , Joseph F. Shepard JR. , Helmut Tews
IPC分类号： H01L021/8242 , H01L021/20
CPC分类号： H01L27/1087
摘要： A method and structure for a fabricating roughened surface walls of a capacitor, such as a deep trench capacitor. The invention starts with a silicon surface and forms silicon germanium grains on the silicon surface. A portion of the silicon surface remains exposed and is etched selective to the silicon germanium grains. The silicon germanium grains are then removed from the silicon surface. The silicon surface is doped after the silicon germanium grains are removed.
摘要翻译：用于制造诸如深沟槽电容器的电容器的粗糙表面壁的方法和结构。本发明从硅表面开始并在硅表面上形成硅锗晶粒。硅表面的一部分保持暴露，并且被选择性地蚀刻到硅锗晶粒上。然后从硅表面除去硅锗晶粒。去除硅锗晶粒后，硅表面被掺杂。

3. 发明申请

US20030207532A1 METHOD AND STRUCTURE FOR SALICIDE TRENCH CAPACITOR PLATE ELECTRODE 失效
标题翻译：硫酸盐电容电极板电极的方法与结构
公开(公告)号：US20030207532A1
公开(公告)日：2003-11-06
申请号：US10137268
申请日：2002-05-01
申请人： International Business Machines Corporation
发明人： Michael Patrick Chudzik , Jack Allan Mandelman , Carl John Radens , Rajarao Jammy , Kenneth T. Settlemyer JR. , Padraic C. Shafer , Joseph F. Shepard JR.
IPC分类号： H01L021/8242
CPC分类号： H01L29/66181 , H01L27/10829 , H01L27/10861 , H01L27/1087 , H01L29/945
摘要： The present invention is a method and structure for fabricating a trench capacitor within a semiconductor substrate having a buried plate electrode formed of metal silicide. A collar is formed in a trench etched into a substrate; a conformal metal film is deposited thereover, and is annealed to form a silicide that is self-aligned to the collar. Silicide will not be formed on the collar, pads and other areas where the silicon is not directly exposed and hence the metal layer can be removed from these areas by selective etching.
摘要翻译：本发明是一种在具有由金属硅化物形成的掩埋板电极的半导体衬底内制造沟槽电容器的方法和结构。在蚀刻到衬底中的沟槽中形成凸缘; 在其上沉积保形金属膜，并对其进行退火以形成与套环自对准的硅化物。硅胶不会形成在硅胶不直接暴露的环，垫和其它区域，因此金属层可以通过选择性蚀刻从这些区域中去除。

4. 发明申请

US20040063277A1 Semiconductor method and structure for simultaneously forming a trench capacitor dielectric and trench sidewall device dielectric 失效
标题翻译：用于同时形成沟槽电容器电介质和沟槽侧壁器件电介质的半导体方法和结构
公开(公告)号：US20040063277A1
公开(公告)日：2004-04-01
申请号：US10260085
申请日：2002-09-27
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Michael P. Chudzik , Rajarao Jammy , Carl John Radens , Kenneth T. Settlemyer JR. , Padraic Shafer , Joseph F. Shepard JR.
IPC分类号： H01L021/8242
CPC分类号： H01L29/66181 , H01L21/3144 , H01L21/31616 , H01L21/31641 , H01L21/31645 , H01L21/31691 , H01L27/10864 , H01L27/10867
摘要： Disclosed herein is a method, in an integrated, of forming a high-K node dielectric of a trench capacitor and a trench sidewall device dielectric at the same time. The method includes forming a trench in a single crystal layer of a semiconductor substrate, and forming an isolation collar along a portion of the trench sidewall, wherein the collar has a top below the top of the trench in the single crystal layer. Then, at the same time, a high-K dielectric is formed along the trench sidewall, the high-K dielectric extending in both an upper portion of the trench including above the isolation collar and in a lower portion of the trench below the isolation collar. The top of the isolation collar is then etched back to expose a portion of the single crystal substrate along the sidewall, and then, a node electrode is formed in conductive contact with the exposed sidewall and also in contact with the high-K dielectric in the lower portion, such that the high-K dielectric remains as a trench sidewall dielectric in the upper portion of the sidewall. In a DRAM memory cell structure, the trench sidewall dielectric may then be used as a gate dielectric of a vertical transistor which accesses the trench storage capacitor in the trench.
摘要翻译：本文公开了一种在同时形成沟槽电容器和沟槽侧壁装置电介质的高K节点电介质的集成方法。所述方法包括在半导体衬底的单晶层中形成沟槽，以及沿着沟槽侧壁的一部分形成隔离环，其中所述环在所述单晶层中具有位于所述沟槽顶部下方的顶部。然后，同时，沿着沟槽侧壁形成高K电介质，高K电介质在包括隔离环的上方的沟槽的上部和隔离环的下方的沟槽的下部延伸。然后隔离环的顶部被回蚀以沿着侧壁露出单晶衬底的一部分，然后，形成与暴露的侧壁导电接触并且还与高K电介质接触的节点电极使得高K电介质保留在侧壁的上部中的沟槽侧壁电介质。在DRAM存储单元结构中，沟槽侧壁电介质可以用作访问沟槽中的沟槽存储电容器的垂直晶体管的栅极电介质。

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