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1. 发明授权

US10671537B2 Reducing translation latency within a memory management unit using external caching structures 审中-公开
公开(公告)号：US10671537B2
公开(公告)日：2020-06-02
申请号：US15682828
申请日：2017-08-22
申请人： International Business Machines Corporation
发明人： Guy L. Guthrie , Jody B. Joyner , Ronald N. Kalla , Michael S. Siegel , Jeffrey A. Stuecheli , Charles D. Wait , Frederick J. Ziegler
IPC分类号： G06F12/0864 , G06F12/1009 , G06F12/0888 , G06F12/0897 , G06F12/1027
摘要： Reducing translation latency within a memory management unit (MMU) using external caching structures including requesting, by the MMU on a node, page table entry (PTE) data and coherent ownership of the PTE data from a page table in memory; receiving, by the MMU, the PTE data, a source flag, and an indication that the MMU has coherent ownership of the PTE data, wherein the source flag identifies a source location of the PTE data; performing a lateral cast out to a local high-level cache on the node in response to determining that the source flag indicates that the source location of the PTE data is external to the node; and directing at least one subsequent request for the PTE data to the local high-level cache.

2. 发明申请

US20200073816A1 SPECULATIVE CHECKIN OF ERAT CACHE ENTRIES 审中-公开
公开(公告)号：US20200073816A1
公开(公告)日：2020-03-05
申请号：US16117099
申请日：2018-08-30
申请人： International Business Machines Corporation
发明人： Bartholomew Blaner , Jay G. Heaslip , Robert D. Herzl , Jody B. Joyner , Jeffrey A. Stuecheli
IPC分类号： G06F12/0897 , G06F12/1009 , G06F12/02
摘要： A method, computer program product, and a computer system are disclosed for processing information in a processor that in one or more embodiments includes setting a threshold number of free Effective to Real Address Translation (ERAT) cache entries in an ERAT cache; determining whether a total number of free ERAT cache entries is less than or equal to the threshold number of free ERAT cache entries; allocating, in response to determining that the total number of free entries is less than or equal to the threshold number, one or more active ERAT cache entries to be speculatively checked in to a memory management unit (MMU); and speculatively checking in the one or more active ERAT cache entries to the MMU.

3. 发明申请

US20150143059A1 DYNAMIC WRITE PRIORITY BASED ON VIRTUAL WRITE QUEUE HIGH WATER MARK 审中-公开
公开(公告)号：US20150143059A1
公开(公告)日：2015-05-21
申请号：US14098563
申请日：2013-12-06
申请人： International Business Machines Corporation
发明人： Benjiman L. Goodman , Jody B. Joyner , Stephen J. Powell , William J. Starke , Jeffrey A. Stuecheli
IPC分类号： G06F12/08
CPC分类号： G06F12/0828 , G06F12/0864 , G06F2212/621 , Y02D10/13
摘要： A set associative cache is managed by a memory controller which places writeback instructions for modified (dirty) cache lines into a virtual write queue, determines when the number of the sets containing a modified cache line is greater than a high water mark, and elevates a priority of the writeback instructions over read operations. The controller can return the priority to normal when the number of modified sets is less than a low water mark. In an embodiment wherein the system memory device includes rank groups, the congruence classes can be mapped based on the rank groups. The number of writes pending in a rank group exceeding a different threshold can additionally be a requirement to trigger elevation of writeback priority. A dirty vector can be used to provide an indication that corresponding sets contain a modified cache line, particularly in least-recently used segments of the corresponding sets.

4. 发明授权

US10649902B2 Reducing translation latency within a memory management unit using external caching structures 有权
公开(公告)号：US10649902B2
公开(公告)日：2020-05-12
申请号：US15819458
申请日：2017-11-21
申请人： International Business Machines Corporation
发明人： Guy L. Guthrie , Jody B. Joyner , Ronald N. Kalla , Michael S. Siegel , Jeffrey A. Stuecheli , Charles D. Wait , Frederick J. Ziegler
IPC分类号： G06F12/0864 , G06F12/1009 , G06F12/0888 , G06F12/0897 , G06F12/1027
摘要： Reducing translation latency within a memory management unit (MMU) using external caching structures including requesting, by the MMU on a node, page table entry (PTE) data and coherent ownership of the PTE data from a page table in memory; receiving, by the MMU, the PTE data, a source flag, and an indication that the MMU has coherent ownership of the PTE data, wherein the source flag identifies a source location of the PTE data; performing a lateral cast out to a local high-level cache on the node in response to determining that the source flag indicates that the source location of the PTE data is external to the node; and directing at least one subsequent request for the PTE data to the local high-level cache.

5. 发明授权

US10599569B2 Maintaining consistency between address translations in a data processing system 有权
公开(公告)号：US10599569B2
公开(公告)日：2020-03-24
申请号：US15190497
申请日：2016-06-23
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Bartholomew Blaner , Jay G. Heaslip , Robert D. Herzl , Jody B. Joyner
IPC分类号： G06F12/00 , G06F12/0831 , G06F12/0808 , G06F12/1027 , G06F12/1009
摘要： A technique for operating a memory management unit (MMU) of a processor includes the MMU detecting that one or more address translation invalidation requests are indicated for an accelerator unit (AU). In response to detecting that the invalidation requests are indicated, the MMU issues a raise barrier request for the AU. In response to detecting a raise barrier response from the AU to the raise barrier request the MMU issues the invalidation requests to the AU. In response to detecting an address translation invalidation response from the AU to each of the invalidation requests, the MMU issues a lower barrier request to the AU. In response to detecting a lower barrier response from the AU to the lower barrier request, the MMU resumes handling address translation check-in and check-out requests received from the AU.

6. 发明授权

US09384136B2 Modification of prefetch depth based on high latency event 有权
标题翻译：基于高延迟事件修改预取深度
公开(公告)号：US09384136B2
公开(公告)日：2016-07-05
申请号：US13861895
申请日：2013-04-12
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： John S Dodson , Miles R. Dooley , Benjiman L. Goodman , Jody B. Joyner , Stephen J. Powell , Eric E. Retter , Jeffrey A. Stuecheli
IPC分类号： G06F12/08 , G06F9/30 , G06F9/38
CPC分类号： G06F12/0862 , G06F9/30047 , G06F9/383
摘要： A prefetch stream is established in a prefetch unit of a memory controller for a system memory at a lowest level of a volatile memory hierarchy of the data processing system based on a memory access request received from a processor core. The memory controller receives an indication of an upcoming high latency event affecting access to the system memory. In response to the indication, the memory controller temporarily increases a prefetch depth of the prefetch stream with respect to the system memory and issues, to the system memory, a plurality of prefetch requests in accordance with the temporarily increased prefetch depth in advance of the upcoming high latency event.
摘要翻译：基于从处理器核心接收的存储器访问请求，在数据处理系统的易失性存储器层级的最低级的系统存储器的存储器控制器的预取单元中建立预取流。存储器控制器接收到影响对系统存储器的访问的即将到来的高等待时间事件的指示。响应于该指示，存储器控制器临时增加相对于系统存储器的预取流的预取深度，并且在即将到来之前根据临时增加的预取深度向系统存储器发出多个预取请求高延迟事件。

7. 发明授权

US09378144B2 Modification of prefetch depth based on high latency event 有权
公开(公告)号：US09378144B2
公开(公告)日：2016-06-28
申请号：US14036284
申请日：2013-09-25
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： John S Dodson , Miles R. Dooley , Benjiman L. Goodman , Jody B. Joyner , Stephen J. Powell , Eric E. Retter , Jeffrey A. Stuecheli
IPC分类号： G06F12/08 , G06F9/30 , G06F9/38
CPC分类号： G06F12/0862 , G06F9/30047 , G06F9/383
摘要： A prefetch stream is established in a prefetch unit of a memory controller for a system memory at a lowest level of a volatile memory hierarchy of the data processing system based on a memory access request received from a processor core. The memory controller receives an indication of an upcoming high latency event affecting access to the system memory. In response to the indication, the memory controller temporarily increases a prefetch depth of the prefetch stream with respect to the system memory and issues, to the system memory, a plurality of prefetch requests in accordance with the temporarily increased prefetch depth in advance of the upcoming high latency event.

8. 发明申请

US20150143056A1 DYNAMIC WRITE PRIORITY BASED ON VIRTUAL WRITE QUEUE HIGH WATER MARK 有权
标题翻译：基于虚拟写水UE UE。。。。。。。。。。。。。。。。。
公开(公告)号：US20150143056A1
公开(公告)日：2015-05-21
申请号：US14082199
申请日：2013-11-18
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Benjiman L. Goodman , Jody B. Joyner , Stephen J. Powell , William J. Starke , Jeffrey A. Stuecheli
IPC分类号： G06F12/08 , G06F12/12
CPC分类号： G06F12/0828 , G06F12/0864 , G06F2212/621 , Y02D10/13
摘要： A set associative cache is managed by a memory controller which places writeback instructions for modified (dirty) cache lines into a virtual write queue, determines when the number of the sets containing a modified cache line is greater than a high water mark, and elevates a priority of the writeback instructions over read operations. The controller can return the priority to normal when the number of modified sets is less than a low water mark. In an embodiment wherein the system memory device includes rank groups, the congruence classes can be mapped based on the rank groups. The number of writes pending in a rank group exceeding a different threshold can additionally be a requirement to trigger elevation of writeback priority. A dirty vector can be used to provide an indication that corresponding sets contain a modified cache line, particularly in least-recently used segments of the corresponding sets.
摘要翻译：集合关联缓存由存储器控制器管理，存储器控制器将修改（脏）高速缓存行的回写指令放入虚拟写入队列中，确定包含修改的高速缓存行的集合的数量何时大于高水位标记，并且升高一个回读指令优先于读取操作。当修改集合的数量小于低水位时，控制器可以将优先级恢复为正常。在其中系统存储器件包括等级组的实施例中，可以基于等级组映射一致等级。超过不同阈值的等级组中挂起的写入次数还可以是触发提高回写优先级的要求。可以使用脏向量来提供对应集合包含修改的高速缓存行的指示，特别是相应集合的最近最少使用的段。

9. 发明申请

US20140372705A1 LEAST-RECENTLY-USED (LRU) TO FIRST-DIRTY-MEMBER DISTANCE-MAINTAINING CACHE CLEANING SCHEDULER 审中-公开
标题翻译：至少最近使用（LRU）到第一个远程会员距离保持缓存清除调度
公开(公告)号：US20140372705A1
公开(公告)日：2014-12-18
申请号：US14033726
申请日：2013-09-23
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Benjiman L. Goodman , Jody B. Joyner , Stephen J. Powell , Aaron C. Sawdey , Jeffrey A. Stuecheli
IPC分类号： G06F12/08
CPC分类号： G06F12/0891 , G06F12/0804 , G06F12/122
摘要： A technique for scheduling cache cleaning operations maintains a clean distance between a set of least-recently-used (LRU) clean lines and the LRU dirty (modified) line for each congruence class in the cache. The technique is generally employed at a victim cache at the highest-order level of the cache memory hierarchy, so that write-backs to system memory are scheduled to avoid having to generate a write-back in response to a cache miss in the next lower-order level of the cache memory hierarchy. The clean distance can be determined by counting all of the LRU clean lines in each congruence class that have a reference count that is less than or equal to the reference count of the LRU dirty line.
摘要翻译：用于调度高速缓存清理操作的技术在高速缓存中的每个同余类之间保持一组最近最近使用（LRU）清洁行和LRU脏（修改）行之间的干净距离。该技术通常在高速缓存存储器层次结构的最高级别的受害者缓存中使用，从而调度系统存储器的回写以避免在下一个较低级别中响应于高速缓存未命中而产生回写缓存内存层次结构的顺序级别。干净的距离可以通过计算每个同余等级的所有LRU干线，其参考计数小于或等于LRU脏线的参考计数。

10. 发明授权

US10884943B2 Speculative checkin of ERAT cache entries 有权
公开(公告)号：US10884943B2
公开(公告)日：2021-01-05
申请号：US16117099
申请日：2018-08-30
申请人： International Business Machines Corporation
发明人： Bartholomew Blaner , Jay G. Heaslip , Robert D. Herzl , Jody B. Joyner , Jeffrey A. Stuecheli
IPC分类号： G06F12/02 , G06F12/0897 , G06F12/1009
摘要： A method, computer program product, and a computer system are disclosed for processing information in a processor that in one or more embodiments includes setting a threshold number of free Effective to Real Address Translation (ERAT) cache entries in an ERAT cache; determining whether a total number of free ERAT cache entries is less than or equal to the threshold number of free ERAT cache entries; allocating, in response to determining that the total number of free entries is less than or equal to the threshold number, one or more active ERAT cache entries to be speculatively checked in to a memory management unit (MMU); and speculatively checking in the one or more active ERAT cache entries to the MMU.

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