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1. 发明授权

US11341060B2 Multifunction communication interface supporting memory sharing among data processing systems 有权
公开(公告)号：US11341060B2
公开(公告)日：2022-05-24
申请号：US16990594
申请日：2020-08-11
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Michael S. Siegel , William J. Starke , Jeffrey A. Stuecheli , Lakshminarayana Arimilli , Kenneth M. Valk , James Mikos , David Krolak
IPC分类号： G06F12/1009 , G06F12/084 , G06F13/16 , G06F12/06
摘要： In a data processing environment, a communication interface of a second host data processing system receives, from a first host data processing system, a host command in a first command set. The host command specifies a memory access to a memory coupled to the second host data processing system. The communication interface translates the host command into a command in a different second command set emulating coupling of an attached functional unit to the communication interface. The communication interface presents the second command to a host bus protocol interface of the second host data processing system. Based on receipt of the second command, the host bus protocol interface initiates, on a system fabric of the second host data processing system, a host bus protocol memory access request specifying the memory access.

2. 发明授权

US10761995B2 Integrated circuit and data processing system having a configurable cache directory for an accelerator 有权
公开(公告)号：US10761995B2
公开(公告)日：2020-09-01
申请号：US16395976
申请日：2019-04-26
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Bartholomew Blaner , Jeffrey A. Stuecheli , Michael S. Siegel , William J. Starke , Curtis C. Wollbrink , Kenneth M. Valk , Lakshminarayana Arimilli , John D. Irish
IPC分类号： G06F12/10 , G06F13/16 , G06F9/38 , G06F12/0817 , G06F12/1027 , G06F12/1045 , G06F3/06 , G06F13/28 , G06F9/455
摘要： An integrated circuit includes a first communication interface for communicatively coupling the integrated circuit with a coherent data processing system, a second communication interface for communicatively coupling the integrated circuit with an accelerator unit including an effective address-based accelerator cache for buffering copies of data from a system memory, and a real address-based directory inclusive of contents of the accelerator cache. The real address-based directory assigns entries based on real addresses utilized to identify storage locations in the system memory. The integrated circuit further includes directory control logic that configures at least a number of congruence classes utilized in the real address-based directory based on configuration parameters specified on behalf of or by the accelerator unit.

3. 发明授权

US10613979B2 Accelerator memory coherency with single state machine 有权
公开(公告)号：US10613979B2
公开(公告)日：2020-04-07
申请号：US15826970
申请日：2017-11-30
申请人： International Business Machines Corporation
发明人： Kenneth M. Valk , Guy L. Guthrie , Derek E. Williams , Michael S. Siegel , John D. Irish
IPC分类号： G06F12/0831 , G06F12/0864
CPC分类号： G06F12/0831 , G06F12/0864 , G06F2212/6032 , G06F2212/621
摘要： A claw-back request, received from an accelerator, is issued for an address line. While waiting for a response to the claw-back request, a cast-out push request with a matching address line is received. The cast-out push request is associated with a cache having a modified copy of the address line. A combined-response, associated with the cast-out push request, is received from a bus. Data associated with the modified copy of the address line is received from the cache. A claw-back response, with the data associated with the modified version of the address line, is issued to an accelerator.

4. 发明授权

US10552351B2 Techniques for issuing interrupts in a data processing system with multiple scopes 有权
公开(公告)号：US10552351B2
公开(公告)日：2020-02-04
申请号：US16254239
申请日：2019-01-22
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Florian A. Auernhammer , Wayne M. Barrett , Robert A. Drehmel , Michael S. Siegel
IPC分类号： G06F13/24
摘要： A technique for handling interrupts in a data processing system includes receiving, by an interrupt routing controller (IRC), an event routing message (ERM) that includes an event source number for a notification source with an unserviced interrupt. In response to receiving the ERM, the IRC builds an event notification message (ENM) based on the event source number. The IRC determines a scope for the ENM based on an event target group (ETG) associated with the event source number. The IRC issues the ENM to an interrupt presentation controller (IPC) at the scope associated with the ETG.

5. 发明申请

US20180349305A1 TECHNIQUES FOR ISSUING INTERRUPTS IN A DATA PROCESSING SYSTEM WITH MULTIPLE SCOPES 审中-公开
公开(公告)号：US20180349305A1
公开(公告)日：2018-12-06
申请号：US15615338
申请日：2017-06-06
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Florian A. Auernhammer , Wayne M. Barrett , Robert A. Drehmel , Michael S. Siegel
IPC分类号： G06F13/24
CPC分类号： G06F13/24 , G06F2213/2412 , G06F2213/2414
摘要： A technique for handling interrupts in a data processing system includes receiving, by an interrupt routing controller (IRC), an event routing message (ERM) that includes an event source number for a notification source with an unserviced interrupt. In response to receiving the ERM, the IRC builds an event notification message (ENM) based on the event source number. The IRC determines a scope for the ENM based on an event target group (ETG) associated with the event source number. The IRC issues the ENM to an interrupt presentation controller (IPC) at the scope associated with the ETG.

6. 发明授权

US09021211B2 Epoch-based recovery for coherent attached processor proxy 有权
标题翻译：相干连接处理器代理的基于时代的恢复
公开(公告)号：US09021211B2
公开(公告)日：2015-04-28
申请号：US13739714
申请日：2013-01-11
申请人： International Business Machines Corporation
发明人： Bartholomew Blaner , Kevin F. Reick , Michael S. Siegel , Jeff A. Stuecheli
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F12/0804 , G06F12/0817 , G06F2212/621
摘要： A coherent attached processor proxy (CAPP) participates in coherence communication in a primary coherent system on behalf of an attached processor external to the primary coherent system. The CAPP includes an epoch timer that advances at regular intervals to define epochs of operation of the CAPP. Each of one or more entries in a data structure in the CAPP are associated with a respective epoch. Recovery operations for the CAPP are initiated based on a comparison of an epoch indicated by the epoch timer and the epoch associated with one of the one or more entries in the data structure.
摘要翻译：连贯的附属处理器代理（CAPP）代表主要相干系统外部的附加处理器参与主要相干系统中的一致性通信。 CAPP包括以规则的间隔前进以定义CAPP的操作时代的时代计时器。 CAPP中数据结构中的一个或多个条目中的每一个都与相应的历元相关联。基于由时序定时器指示的时期与与数据结构中的一个或多个条目之一相关联的历元的比较，开始CAPP的恢复操作。

7. 发明授权

US08990513B2 Accelerated recovery for snooped addresses in a coherent attached processor proxy 有权
标题翻译：在连贯的连接处理器代理中侦听地址的加速恢复
公开(公告)号：US08990513B2
公开(公告)日：2015-03-24
申请号：US13739770
申请日：2013-01-11
申请人： International Business Machines Corporation
发明人： Bartholomew Blaner , David W. Cummings , George W. Daly, Jr. , Michael S. Siegel , Jeff A. Stuecheli
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F12/0804 , G06F12/0817 , G06F2212/621
摘要： A coherent attached processor proxy (CAPP) that participates in coherence communication in a primary coherent system on behalf of an external attached processor maintains, in each of a plurality of entries of a CAPP directory, information regarding a respective associated cache line of data from the primary coherent system cached by the attached processor. In response to initiation of recovery operations, the CAPP transmits, in a generally sequential order with respect to the CAPP directory, multiple memory access requests indicating an error for addresses indicated by the plurality of entries. In response to a snooped memory access request that targets a particular address hitting in the CAPP directory during the transmitting, the CAPP performs a coherence recovery operation for the particular address prior to a time indicated by the generally sequential order.
摘要翻译：在主要相干系统中代表外部附加处理器参与相干通信的相干附加处理器代理（CAPP）在CAPP目录的多个条目的每一个中维护关于来自由连接的处理器缓存的主要相干系统。响应于启动恢复操作，CAPP相对于CAPP目录以大致顺序的顺序发送指示由多个条目指示的地址的错误的多个存储器访问请求。响应于在发送期间针对在CAPP目录中的特定地址的窥探存储器访问请求，CAPP在由大致顺序的顺序指示的时间之前对特定地址执行相干恢复操作。

8. 发明申请

US20140379997A1 COHERENT ATTACHED PROCESSOR PROXY HAVING HYBRID DIRECTORY 有权
标题翻译：具有混合目录的相关附件处理器代码
公开(公告)号：US20140379997A1
公开(公告)日：2014-12-25
申请号：US13921844
申请日：2013-06-19
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Bartholomew Blaner , Michael S. Siegel , Jeffrey A. Stuecheli , Charles F. Marino
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F12/082 , G06F2212/621
摘要： A coherent attached processor proxy (CAPP) includes transport logic having a first interface configured to support communication with a system fabric of a primary coherent system and a second interface configured to support communication with an attached processor (AP) that is external to the primary coherent system and that includes a cache memory that holds copies of memory blocks belonging to a coherent address space of the primary coherent system. The CAPP further includes one or more master machines that initiate memory access requests on the system fabric of the primary coherent system on behalf of the AP, one or more snoop machines that service requests snooped on the system fabric, and a CAPP directory having a precise directory having a plurality of entries each associated with a smaller data granule and a coarse directory having a plurality of entries each associated with a larger data granule.
摘要翻译：相干连接处理器代理（CAPP）包括传输逻辑，其具有被配置为支持与主相干系统的系统结构的通信的第一接口和被配置为支持与主要相干系统外部的附接处理器（AP）的通信的第二接口的传输逻辑并且其包括保存属于主要相干系统的相干地址空间的存储器块的副本的高速缓冲存储器。 CAPP还包括一个或多个主机，其代表AP发起主相干系统的系统结构上的存储器访问请求，在系统结构上监视服务请求的一个或多个窥探机，以及具有精确目录具有多个条目，每个条目与较小的数据粒子相关联，粗略目录具有多个条目，每个条目与较大的数据粒子相关联。

9. 发明申请

US20140201465A1 ACCELERATED RECOVERY FOR SNOOPED ADDRESSES IN A COHERENT ATTACHED PROCESSOR PROXY 有权
公开(公告)号：US20140201465A1
公开(公告)日：2014-07-17
申请号：US14036109
申请日：2013-09-25
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Bartholomew Blaner , David W. Cummings , George W. Daly, JR. , Michael S. Siegel , Jeff A. Stuecheli
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F12/0804 , G06F12/0817 , G06F2212/621
摘要： A coherent attached processor proxy (CAPP) that participates in coherence communication in a primary coherent system on behalf of an external attached processor maintains, in each of a plurality of entries of a CAPP directory, information regarding a respective associated cache line of data from the primary coherent system cached by the attached processor. In response to initiation of recovery operations, the CAPP transmits, in a generally sequential order with respect to the CAPP directory, multiple memory access requests indicating an error for addresses indicated by the plurality of entries. In response to a snooped memory access request that targets a particular address hitting in the CAPP directory during the transmitting, the CAPP performs a coherence recovery operation for the particular address prior to a time indicated by the generally sequential order.

10. 发明授权

US11449489B2 Split transaction coherency protocol in a data processing system 有权
公开(公告)号：US11449489B2
公开(公告)日：2022-09-20
申请号：US15807828
申请日：2017-11-09
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Bernard C. Drerup , Guy L. Guthrie , Michael S. Siegel , Jeffrey A. Stuecheli
IPC分类号： G06F16/23 , G06F16/24 , G06F9/46
摘要： A technique for operating a data processing system that implements a split transaction coherency protocol that has an address tenure and a data tenure includes receiving, at a data source, a command (that includes an address tenure for requested data) that is issued from a data sink. The data source issues a response that indicates data associated with the address tenure is available to be transferred to the data sink during a data tenure. In response to determining that the data is available subsequent to issuing the response, the data source issues a first data packet to the data sink that includes the data during the data tenure. In response to determining that the data is not available subsequent to issuing the response, the data source issues a second data packet to the data sink that includes a data header that indicates the data is unavailable.

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