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1. 发明授权

US11620154B2 Suppressing interrupts to an application thread 有权
公开(公告)号：US11620154B2
公开(公告)日：2023-04-04
申请号：US16732856
申请日：2020-01-02
申请人： International Business Machines Corporation
发明人： Dirk Michel , Bret R. Olszewski , Matthew R. Ochs
IPC分类号： G06F9/48
摘要： In a computing system, an application thread is executed on a hardware thread. Based on a configuration of the computing system, a first threshold is determined comprising a threshold percentage of execution time spent servicing a set of interrupts to the application thread relative to a total execution time for the hardware thread. For the hardware thread, a length of a first time period spent servicing an interrupt in the set of interrupts and a length of a second time period spent executing the application thread are measured. A cumulative percentage of execution time spent in the first time period relative to execution time spent in the first time period and the second time period is calculated. Responsive to the cumulative percentage being above the threshold percentage, interrupt servicing on the hardware thread is disabled.

2. 发明申请

US20200301735A1 HARDWARE THREAD SWITCHING FOR SCHEDULING POLICY IN A PROCESSOR 审中-公开
公开(公告)号：US20200301735A1
公开(公告)日：2020-09-24
申请号：US16356348
申请日：2019-03-18
申请人： International Business Machines Corporation
发明人： Mathew Accapadi , Chad Collie , Grover C. Davidson, II , Dirk Michel , Bret R. Olszewski
IPC分类号： G06F9/48
摘要： Examples of techniques for hardware thread switching for scheduling policy in a processor are described herein. An aspect includes, based on receiving a request from a first software thread to dispatch to a first hardware thread, determining that the first hardware thread is occupied by a second software thread that has a higher priority than the first software thread. Another aspect includes issuing an interrupt to switch the second software thread from the first hardware thread to a second hardware thread. Another aspect includes, based on switching of the second software thread from the first hardware thread to the second hardware thread, dispatching the first software thread to the first hardware thread.

3. 发明申请

US20180157304A1 PROCESSOR MANAGEMENT VIA THREAD STATUS 审中-公开
公开(公告)号：US20180157304A1
公开(公告)日：2018-06-07
申请号：US15888037
申请日：2018-02-04
申请人： International Business Machines Corporation
发明人： Bernard A. King-Smith , Bret R. Olszewski , Stephen Rees , Basu Vaidyanathan
IPC分类号： G06F1/32 , G06F9/48
CPC分类号： G06F1/3228 , G06F1/3296 , G06F9/4843 , Y02B70/1441 , Y02D10/24
摘要： A process for processor management includes activating a delay thread running on a processor. A determination is made whether a wait event for a first thread running on the processor is in a queue. Responsive to determining that the wait event for the first thread is in the queue, a determination is made whether a wait time associated with the wait event has expired. Responsive to determining that the wait time has not expired, a determination is made if wait time exceeds a threshold. Responsive to determining that the wait time exceeds the threshold, a timer is set and a low power mode is initiated for the processor.

4. 发明授权

US09928157B2 Filtering multiple in-memory trace buffers for event ranges before dumping from memory 有权
公开(公告)号：US09928157B2
公开(公告)日：2018-03-27
申请号：US14552942
申请日：2014-11-25
申请人： International Business Machines Corporation
发明人： Mathew Accapadi , Grover C. Davidson, II , Dirk Michel , Bret R. Olszewski
IPC分类号： G06F11/36
CPC分类号： G06F11/3636
摘要： A method for filtering multiple in-memory trace buffers for event ranges is provided. The method includes allocating a plurality of main trace buffers, based on the number of central processing units (CPU) participating in a trace. Each CPU has a dedicated main trace buffer, and each main trace buffer is circular. Each main trace buffer is divided into an equal number of sub-buffers. A plurality of events is written to the current sub-buffer. When the current sub-buffer is filled, events are written to the next sub-buffer. Events are extracted from at least one of the sub-buffers, starting with the sub-buffer that includes a compare time and ending at the end of the main trace buffer.

5. 发明授权

US09886077B2 Processor management via thread status 有权
公开(公告)号：US09886077B2
公开(公告)日：2018-02-06
申请号：US15150193
申请日：2016-05-09
申请人： International Business Machines Corporation
发明人： Bernard A. King-Smith , Bret R. Olszewski , Stephen Rees , Basu Vaidyanathan
IPC分类号： G06F9/455 , G06F9/46 , G06F1/32 , G06F9/48
CPC分类号： G06F1/3228 , G06F1/3296 , G06F9/4843 , Y02B70/1441 , Y02D10/24
摘要： Various systems, processes, and products may be used to manage a processor. In particular implementations, managing a processor may include the ability to determine whether a thread is pausing for a short period of time and place a wait event for the thread in a queue based on a short thread pause occurring. Managing a processor may also include the ability to activate a delay thread that determines whether a wait time associated with the pause has expired and remove the wait event from the queue based on the wait time having expired.

6. 发明申请

US20170132127A1 Optimized Use of Hardware Micro Partition Prefetch Based on Software Thread Usage 有权
公开(公告)号：US20170132127A1
公开(公告)日：2017-05-11
申请号：US14949924
申请日：2015-11-24
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Hemalatha B T , Peter J. Heyrman , Bret R. Olszewski
IPC分类号： G06F12/08 , G06F9/455
CPC分类号： G06F12/084 , G06F9/45558 , G06F9/5077 , G06F12/0808 , G06F12/0873 , G06F12/0895 , G06F2009/45583 , G06F2009/45595 , G06F2212/1041 , G06F2212/1044 , G06F2212/151 , G06F2212/152 , G06F2212/281 , G06F2212/452 , G06F2212/608
摘要： A computer-implemented method selectively adjusts a resources addresses cache of addresses of resources used by virtual processors. A first dispatch from a hypervisor dispatches a first virtual processor, and then tracks processes executed by the first virtual processor. The hypervisor caches cache addresses of resources used by the processes after the first dispatch in a resources addresses cache. The hypervisor undispatches the first virtual processor, and then redispatches the first virtual processor as a second virtual processor by issuing a second dispatch. Processes executed by the second virtual processor are compared to processes executed during by the first virtual processor, thus leading to an identification of a level of process utilization consistency. The hypervisor then adjusts the resources addresses cache by selectively clearing resource addresses based on the level of process utilization consistency.

7. 发明授权

US09465807B2 Management of file cache 有权
标题翻译：管理文件缓存
公开(公告)号：US09465807B2
公开(公告)日：2016-10-11
申请号：US14057716
申请日：2013-10-18
申请人： International Business Machines Corporation
发明人： Mathew Accapadi , Grover C. Davidson, II , Dirk Michel , Bret R. Olszewski
IPC分类号： G06F17/30 , G06F12/08 , G06F12/12
CPC分类号： G06F17/30132 , G06F12/0891 , G06F12/126 , G06F12/127 , G06F17/30067 , G06F2212/463
摘要： A method and computer program product for managing a file cache with a filesystem cache manager is disclosed. The method may include installing the filesystem cache manager for the file cache by a mount command. The filesystem cache manager may include a specified time interval and a first cache elimination instruction. The method may further include starting a first timer upon the installation of the filesystem cache manager. The method may further include running the first cache elimination instruction when the first timer reaches the specified time interval.
摘要翻译：公开了一种用于使用文件系统高速缓存管理器来管理文件高速缓存的方法和计算机程序产品。该方法可以包括通过安装命令安装用于文件高速缓存的文件系统高速缓存管理器。文件系统高速缓存管理器可以包括指定的时间间隔和第一高速缓存消除指令。该方法还可以包括在安装文件系统高速缓存管理器时启动第一定时器。该方法还可以包括当第一定时器到达指定的时间间隔时运行第一高速缓存消除指令。

8. 发明申请

US20160147653A1 FILTERING MULTIPLE IN-MEMORY TRACE BUFFERS FOR EVENT RANGES BEFORE DUMPING FROM MEMORY 有权
标题翻译：在从存储器中删除事件范围之前过滤多个内存跟踪缓冲区
公开(公告)号：US20160147653A1
公开(公告)日：2016-05-26
申请号：US14552942
申请日：2014-11-25
申请人： International Business Machines Corporation
发明人： Mathew Accapadi , Grover C. Davidson, II , Dirk Michel , Bret R. Olszewski
IPC分类号： G06F12/06
CPC分类号： G06F11/3636
摘要： A method for filtering multiple in-memory trace buffers for event ranges is provided. The method includes allocating a plurality of main trace buffers, based on the number of central processing units (CPU) participating in a trace. Each CPU has a dedicated main trace buffer, and each main trace buffer is circular. Each main trace buffer is divided into an equal number of sub-buffers. A plurality of events is written to the current sub-buffer. When the current sub-buffer is filled, events are written to the next sub-buffer. Events are extracted from at least one of the sub-buffers, starting with the sub-buffer that includes a compare time and ending at the end of the main trace buffer.
摘要翻译：提供了一种过滤用于事件范围的多个内存中跟踪缓冲区的方法。该方法包括基于参与跟踪的中央处理单元（CPU）的数量分配多个主跟踪缓冲器。每个CPU都有一个专用的主跟踪缓冲区，每个主跟踪缓冲区是循环的。每个主跟踪缓冲区被分成相等数量的子缓冲区。多个事件被写入当前子缓冲器。当当前子缓冲区被填满时，事件被写入下一个子缓冲区。从至少一个子缓冲器提取事件，从包括比较时间并在主跟踪缓冲器的末尾结束的子缓冲器开始。

9. 发明申请

US20150113226A1 MANAGEMENT OF FILE CACHE 有权
公开(公告)号：US20150113226A1
公开(公告)日：2015-04-23
申请号：US14098061
申请日：2013-12-05
申请人： International Business Machines Corporation
发明人： Mathew Accapadi , Grover C. Davidson, II , Dirk Michel , Bret R. Olszewski
IPC分类号： G06F17/30 , G06F12/08
CPC分类号： G06F17/30132 , G06F12/0891 , G06F12/126 , G06F12/127 , G06F17/30067 , G06F2212/463
摘要： A method and computer program product for managing a file cache with a filesystem cache manager is disclosed. The method may include installing the filesystem cache manager for the file cache by a mount command. The filesystem cache manager may include a specified time interval and a first cache elimination instruction. The method may further include starting a first timer upon the installation of the filesystem cache manager. The method may further include running the first cache elimination instruction when the first timer reaches the specified time interval.

10. 发明授权

US08954974B1 Adaptive lock list searching of waiting threads 有权
标题翻译：等待线程的自适应锁列表搜索
公开(公告)号：US08954974B1
公开(公告)日：2015-02-10
申请号：US14076223
申请日：2013-11-10
申请人： International Business Machines Corporation
发明人： Mathew Accapadi , Grover C. Davidson, II , Dirk Michel , Bret R. Olszewski
IPC分类号： G06F9/46 , G06F9/52
CPC分类号： G06F9/52 , G06F9/524 , G06F9/526
摘要： A system and technique for adaptive lock list searching of waiting threads includes logic executable by a processor to: determine an average service time for a lock associated with a shared computing resource; determine an average search time for selecting a thread to next receive the lock from a plurality of threads waiting for the lock; sum the average service time and the average search time; apply a search factor to the summed average service time and average search time to obtain a target search time for searching the waiting threads for selecting the next thread for obtaining the lock; determine a quantity of waiting threads to consider for next obtaining the lock based on the target search time and the average search time, the quantity being less than a total quantity of waiting threads; and identify the next thread to obtain the lock from the quantity.
摘要翻译：用于等待线程的自适应锁列表搜索的系统和技术包括可由处理器执行的逻辑：确定与共享计算资源相关联的锁的平均服务时间; 确定用于选择线程以接下来从等待锁定的多个线程接收锁定的平均搜索时间; 求平均服务时间和平均搜索时间; 将搜索因子应用于求和的平均服务时间和平均搜索时间，以获得用于搜索等待线程以选择下一个线程以获得锁定的目标搜索时间; 基于目标搜索时间和平均搜索时间确定下一次获取锁的等待线程数量，该数量小于等待线程的总数; 并确定从数量获取锁的下一个线程。

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