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1. 发明申请

US20190332549A1 INTEGRATED CIRCUIT AND DATA PROCESSING SYSTEM HAVING A CONFIGURABLE CACHE DIRECTORY FOR AN ACCELERATOR 审中-公开
公开(公告)号：US20190332549A1
公开(公告)日：2019-10-31
申请号：US16395976
申请日：2019-04-26
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： BARTHOLOMEW BLANER , JEFFREY A. STUECHELI , MICHAEL S. SIEGEL , WILLIAM J. STARKE , CURTIS C. WOLLBRINK , KENNETH M. VALK , LAKSHMINARAYANA ARIMILLI , JOHN D. IRISH
IPC分类号： G06F12/10 , G06F13/16
摘要： An integrated circuit includes a first communication interface for communicatively coupling the integrated circuit with a coherent data processing system, a second communication interface for communicatively coupling the integrated circuit with an accelerator unit including an effective address-based accelerator cache for buffering copies of data from a system memory, and a real address-based directory inclusive of contents of the accelerator cache. The real address-based directory assigns entries based on real addresses utilized to identify storage locations in the system memory. The integrated circuit further includes directory control logic that configures at least a number of congruence classes utilized in the real address-based directory based on configuration parameters specified on behalf of or by the accelerator unit.

2. 发明申请

US20140250275A1 SELECTION OF POST-REQUEST ACTION BASED ON COMBINED RESPONSE AND INPUT FROM THE REQUEST SOURCE 有权
公开(公告)号：US20140250275A1
公开(公告)日：2014-09-04
申请号：US13781932
申请日：2013-03-01
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： BARTHOLOMEW BLANER , DAVID W. CUMMINGS , BRIAN FLACHS , MICHAEL S. SIEGEL , JEFFREY A. STUECHELI
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F12/0815
摘要： A data structure includes a plurality of entries each corresponding to a different systemwide combined response of a data processing system. A particular entry includes identifiers of multiple possible actions that can be taken in response to a systemwide combined response. Master logic issues a memory access request on a system fabric of the data processing system. The master logic, responsive to receiving the systemwide combined response and a selection of one of the multiple possible actions from a source of the memory access request prior to receipt of the systemwide combined response, selects the particular entry based on the systemwide combined response and selects one of the multiple possible actions identified in the particular entry based on the received selection. The master logic services the memory access request in accordance with the systemwide combined response by performing the selected one of the multiple possible actions.

3. 发明申请

US20140149683A1 PROGRAMMABLE COHERENT PROXY FOR ATTACHED PROCESSOR 审中-公开
标题翻译：可编程处理器的可编程代码
公开(公告)号：US20140149683A1
公开(公告)日：2014-05-29
申请号：US13777028
申请日：2013-02-26
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： BARTHOLOMEW BLANER , DAVID W. CUMMINGS , MICHAEL S. SIEGEL , WILLIAM J. STARKE , JEFF A. STUECHELI
IPC分类号： G06F12/08
CPC分类号： G06F12/0815 , G06F3/122 , G06F12/0284 , G06F12/0638 , G06F12/082 , G06F12/0831 , G06F12/1416 , G06F13/1615
摘要： A coherent attached processor proxy (CAPP) within a primary coherent system participates in an operation on a system fabric of the primary coherent system on behalf of an attached processor (AP) that is external to the primary coherent system and that is coupled to the CAPP. The operation includes multiple components communicated with the CAPP including a request and at least one coherence message. The CAPP determines one or more of the components of the operation by reference to at least one programmable data structure within the CAPP that can be reprogrammed.
摘要翻译：主要相干系统内的相干附属处理器代理（CAPP）代表主要相干系统外部的附加处理器（AP）参与主要相干系统的系统结构的操作，并且耦合到CAPP 。该操作包括与CAPP通信的多个组件，包括请求和至少一个连贯消息。 CAPP通过参考可重新编程的CAPP内的至少一个可编程数据结构来确定操作的一个或多个组件。

4. 发明申请

US20190332548A1 TRANSLATION INVALIDATION IN A TRANSLATION CACHE SERVING AN ACCELERATOR 审中-公开
公开(公告)号：US20190332548A1
公开(公告)日：2019-10-31
申请号：US16388478
申请日：2019-04-18
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： BARTHOLOMEW BLANER , MICHAEL S. SIEGEL , JEFFREY A. STUECHELI , WILLIAM J. STARKE , KENNETH M. VALK , JOHN D. IRISH , LAKSHMINARAYANA ARIMILLI
IPC分类号： G06F12/10 , G06F3/06 , G06F13/28
摘要： An integrated circuit includes a first communication interface for communicatively coupling the integrated circuit with a coherent data processing system, a second communication interface for communicatively coupling the integrated circuit with an accelerator unit including an accelerator functional unit and an effective address-based accelerator cache for buffering copies of data from the system memory of the coherent data processing system, and a real address-based directory inclusive of contents of the accelerator cache. The real address-based directory assigns entries based on real addresses utilized to identify storage locations in the system memory. The integrated circuit includes request logic that, responsive to receipt on the first communication interface of a translation entry invalidation request, issues to the accelerator unit via the second communication interface an invalidation request that identifies an entry in the effective address-based accelerator cache to be invalidated utilizing a host tag identifying a storage location in the real address-based directory.

5. 发明申请

US20180052688A1 MEMORY MOVE INSTRUCTION SEQUENCE TARGETING AN ACCELERATOR SWITCHBOARD 审中-公开
公开(公告)号：US20180052688A1
公开(公告)日：2018-02-22
申请号：US15243650
申请日：2016-08-22
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： LAKSHMINARAYANA B. ARIMILLI , BARTHOLOMEW BLANER , WILLIAM J. STARKE , RANDAL C. SWANBERG , SCOTT M. WILLENBORG
IPC分类号： G06F9/30 , G06F12/0875
CPC分类号： G06F9/30032 , G06F9/30043 , G06F12/0811 , G06F12/0831 , G06F12/0875 , G06F12/0879 , G06F12/1081 , G06F2212/1016 , G06F2212/1048 , G06F2212/206 , G06F2212/452
摘要： A processor core of a data processing system, in response to a first instruction, generates a copy-type request specifying a source real address and transmits it to a lower level cache. In response to a second instruction, the processor core generates a paste-type request specifying a destination real address associated with a memory-mapped device and transmits it to the lower level cache. In response to the copy-type request, the lower level cache copies a data granule from a storage location specified by the source real address into a non-architected buffer. In response to the paste-type request, the lower level cache writes the data granule from the non-architected buffer to the memory-mapped device. In response to receipt of the data granule, the memory-mapped device stores the data granule in a queue in the system memory associated with a hardware device of the data processing system.

6. 发明申请

US20140365733A1 INTEGRATED CIRCUIT SYSTEM HAVING DECOUPLED LOGICAL AND PHYSICAL INTERFACES 审中-公开
标题翻译：具有解码逻辑和物理接口的集成电路系统
公开(公告)号：US20140365733A1
公开(公告)日：2014-12-11
申请号：US14465516
申请日：2014-08-21
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： BARTHOLOMEW BLANER , CHARLES MARINO , MICHAEL S. SIEGEL , WILLIAM J. STARKE , JEFF A. STUECHELI
IPC分类号： G06F12/08
CPC分类号： G06F12/0822 , G06F12/0831 , G06F2212/622
摘要： An integrated circuit system including a first integrated circuit chip including first logic, a second integrated circuit chip, and second logic distributed across the first and second integrated circuit chips. The second logic includes a first unit integrated in the first integrated circuit chip and a second unit integrated in the second integrated circuit chip. The integrated circuit system further includes a physical communication link coupling the first unit in the first integrated circuit chip and the second unit in the second integrated circuit chip and a request interface between the first logic and first unit of the second logic. The request interface is implemented in the first integrated circuit such that communication via the request interface between the first logic and the first unit of the second logic has low latency and such that the request interface is decoupled from the physical communication link.
摘要翻译：一种集成电路系统，包括第一集成电路芯片，包括第一逻辑，第二集成电路芯片和分布在第一和第二集成电路芯片上的第二逻辑。第二逻辑包括集成在第一集成电路芯片中的第一单元和集成在第二集成电路芯片中的第二单元。集成电路系统还包括耦合第一集成电路芯片中的第一单元和第二集成电路芯片中的第二单元的物理通信链路以及第二逻辑的第一逻辑与第一单元之间的请求接口。请求接口在第一集成电路中实现，使得经由第一逻辑和第二逻辑的第一单元之间的请求接口的通信具有低等待时间，并且使得请求接口与物理通信链路分离。

7. 发明申请

US20140201466A1 DATA RECOVERY FOR COHERENT ATTACHED PROCESSOR PROXY 有权
标题翻译：数据恢复用于相互连接的处理器代码
公开(公告)号：US20140201466A1
公开(公告)日：2014-07-17
申请号：US14035470
申请日：2013-09-24
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： BARTHOLOMEW BLANER , KENNETH A. LAURICELLA , JOSEPH G. MCDONALD , MICHAEL S. SIEGEL , JEFF A. STUECHELI
IPC分类号： G06F12/08
CPC分类号： G06F12/0815 , G06F12/082 , G06F12/0831
摘要： A coherent attached processor proxy (CAPP) that participates in coherence communication in a primary coherent system on behalf of an attached processor external to the primary coherent system tracks delivery of data to destinations in the primary coherent system via one or more entries in a data structure. Each of the one or more entries specifies with a destination tag a destination in the primary coherent system to which data is to be delivered from the attached processor. In response to initiation of recovery operations for the CAPP, the CAPP performs data recovery operations, including transmitting, to at least one destination indicated by the destination tag of one or more entries, an indication of a data error in data to be delivered to that destination from the attached processor.
摘要翻译：参与主要相干系统中的相干连接代理（CAPP）代表主要相干系统外部的附加处理器通过数据结构中的一个或多个条目跟踪数据传送到主要相干系统中的目的地。一个或多个条目中的每个条目将目的地标签指定为要从所附加的处理器传送数据的主要相干系统中的目的地。响应于CAPP的恢复操作的启动，CAPP执行数据恢复操作，包括向至少一个目的地标签指示的至少一个目的地传送一个或多个条目的数据错误的指示，该数据错误将被传送到该数据来自附属处理器的目的地。

8. 发明申请

US20190065493A1 EFFICIENT AND ACCURATE LOOKUPS OF DATA BY A STREAM PROCESSOR USING A HASH TABLE 审中-公开
公开(公告)号：US20190065493A1
公开(公告)日：2019-02-28
申请号：US15688493
申请日：2017-08-28
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： BULENT ABALI , BARTHOLOMEW BLANER , JOHN J. REILLY
IPC分类号： G06F17/30 , G06F12/02 , G06F12/0866
CPC分类号： G06F16/2255 , G06F12/0246 , G06F12/0866 , G06F16/90344 , H04L67/2828
摘要： Responsive to a data lookup in a buffer triggered for a search string, a processor searches for a selection of pairs from among multiple pairs of a hash table read from at least one address hash of the search string and matching at least one data hash of the search string, each row of the hash table assigned to a separate address hash, each of the pairs comprising a pointer to a location in the buffer and a tag with a previous data hash of a previously buffered string in the buffer. The processor identifies, from among the selection of pairs, at least one separate location in the buffer most frequently pointed to by two or more pointers within the selection of pairs. The processor, responsive to at least one read string from the buffer at the at least one separate location matching at least a substring of the search string, outputs the at least one separate location as the response to the data lookup.

9. 发明申请

US20180150396A1 MANAGING LOWEST POINT OF COHERENCY (LPC) MEMORY USING A SERVICE LAYER ADAPTER 审中-公开
公开(公告)号：US20180150396A1
公开(公告)日：2018-05-31
申请号：US15364458
申请日：2016-11-30
申请人： International Business Machines Corporation
发明人： ETAI ADAR , LAKSHMINARAYANA B. ARIMILLI , YIFTACH BENJAMINI , BARTHOLOMEW BLANER , WILLIAM J. STARKE , JEFFREY A. STUECHELI
IPC分类号： G06F12/0815 , G06F12/1081 , G06F12/14
CPC分类号： G06F12/0815 , G06F12/1081 , G06F12/145 , G06F13/1668 , G06F2212/1024 , G06F2212/1052 , G06F2212/621 , G06F2212/656
摘要： Managing lowest point of coherency (LPC) memory using a service layer adapter, the adapter coupled to a processor and an accelerator on a host computing system, the processor configured for symmetric multi-processing, including receiving, by the adapter, a memory access instruction from the accelerator; retrieving, by the adapter, a real address for the memory access instruction; determining, using base address registers on the adapter, that the real address targets the LPC memory, wherein the base address registers direct memory access requests between the LPC memory and other memory locations on the host computing system; and sending, by the adapter, the memory access instruction and the real address to a media controller for the LPC memory, wherein the media controller for the LPC memory is attached to the adapter via a memory interface.

10. 发明申请

US20140201460A1 DATA RECOVERY FOR COHERENT ATTACHED PROCESSOR PROXY 有权
公开(公告)号：US20140201460A1
公开(公告)日：2014-07-17
申请号：US13739525
申请日：2013-01-11
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： BARTHOLOMEW BLANER , KENNETH A. LAURICELLA , JOSEPH G. MCDONALD , MICHAEL S. SIEGEL , JEFF A. STUECHELI
IPC分类号： G06F12/08
CPC分类号： G06F12/0815 , G06F12/082 , G06F12/0831
摘要： A coherent attached processor proxy (CAPP) that participates in coherence communication in a primary coherent system on behalf of an attached processor external to the primary coherent system tracks delivery of data to destinations in the primary coherent system via one or more entries in a data structure. Each of the one or more entries specifies with a destination tag a destination in the primary coherent system to which data is to be delivered from the attached processor. In response to initiation of recovery operations for the CAPP, the CAPP performs data recovery operations, including transmitting, to at least one destination indicated by the destination tag of one or more entries, an indication of a data error in data to be delivered to that destination from the attached processor.

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