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1. 发明授权

US06535447B2 Semiconductor memory device and voltage level control method thereof 失效
公开(公告)号：US06535447B2
公开(公告)日：2003-03-18
申请号：US10000178
申请日：2001-11-30
申请人： Hyung-Dong Kim , Kwang-Hyun Kim
发明人： Hyung-Dong Kim , Kwang-Hyun Kim
IPC分类号： G11C700
CPC分类号： G05F3/242
摘要： The present invention discloses a semiconductor memory device and a voltage level control method thereof. The semiconductor memory device comprises multiple sub high voltage generators, multiple control circuits, a high voltage level detecting circuit, and a mode setting circuit. The multiple sub high voltage generators boost the high voltage level. The multiple control circuits control operations of each of the corresponding multiple sub high voltage generators responsive to each of corresponding high voltage detecting signals and to each of corresponding multiple control signals in the test mode. The high voltage level detecting circuit enabled by an active signal, detects the level drop of a high voltage and generates the high voltage detecting signal. The mode setting circuit sets the state of the multiple control signals responsive to the signals from the out side in the test mode. Performing the test by regulating the number of the multiple sub high voltage generators can prevent the semiconductor memory device from over kill. In addition, the test of the package state can be performed by enabling a few of the voltage generators than necessary for the full operation of the test mode.

2. 发明授权

US09076360B2 Display apparatus for displaying an image in a 2D mode and a 3D mode using a patterned retarder 有权
标题翻译：用2D显示图像的显示装置和使用图案化延迟器的3D模式
公开(公告)号：US09076360B2
公开(公告)日：2015-07-07
申请号：US13340402
申请日：2011-12-29
申请人： Taeho Kim , Sang-Jae Kim , Kwang-Hyun Kim , Daewon Kim , Ji-Hoon Kim , Seungbeom Park , Beong-hun Beon , Seunghee Lee , GwanYoung Na
发明人： Taeho Kim , Sang-Jae Kim , Kwang-Hyun Kim , Daewon Kim , Ji-Hoon Kim , Seungbeom Park , Beong-hun Beon , Seunghee Lee , GwanYoung Na
IPC分类号： G02F1/1335 , G09G3/00 , G09G3/36
CPC分类号： G09G3/003 , G09G3/3648 , G09G2300/0426 , G09G2300/0443
摘要： A display apparatus including a display panel and a patterned retarder disposed on the display panel. The display apparatus displays a first image in a 2D mode and displays a second image including a left-eye image and a right-eye image in a 3D mode. Each of the sub-pixels included in the display panel includes two or three sub-pixel electrodes, and the patterned retarder includes a first retarder and a second retarder, which provide different directivities from each other to the left-eye image and the right-eye image, respectively. The first retarder is disposed corresponding to at least a portion of the sub-pixels and the second retarder is disposed corresponding to a remaining portion of the sub-pixels.
摘要翻译：一种显示装置，包括设置在显示面板上的显示面板和图案化延迟器。显示装置以2D模式显示第一图像，并且以3D模式显示包括左眼图像和右眼图像的第二图像。包括在显示面板中的每个子像素包括两个或三个子像素电极，并且图案化延迟器包括第一延迟器和第二延迟器，其向左眼图像和右眼图像提供彼此不同的方向性，眼睛图像。第一延迟器对应于子像素的至少一部分设置，并且第二延迟器对应于子像素的剩余部分设置。

3. 发明授权

US08305819B2 Data output circuit of semiconductor memory device 有权
标题翻译：半导体存储器件的数据输出电路
公开(公告)号：US08305819B2
公开(公告)日：2012-11-06
申请号：US12751425
申请日：2010-03-31
申请人： Kwang-Hyun Kim , Kang-Youl Lee
发明人： Kwang-Hyun Kim , Kang-Youl Lee
IPC分类号： G11C7/10
CPC分类号： G11C7/00 , G11C7/10
摘要： A data output circuit of a semiconductor memory device includes a pipe latch unit configured to store input parallel data and align the stored data in response to a plurality of alignment control signals to output serial output data, and an alignment control signal generating unit configured to generate the plurality of alignment control signals in response to a burst-type information and a seed address group, wherein the alignment control signal generating unit generates the alignment control signals to swap data in a swap mode where the burst-type is a certain type and bits of the seed address group are certain values.
摘要翻译：一种半导体存储器件的数据输出电路，包括配置为存储输入并行数据并响应于多个对准控制信号对准存储的数据以输出串行输出数据的管锁存单元，以及对准控制信号生成单元，所述多个对准控制信号响应于突发类型信息和种子地址组，其中所述对准控制信号生成单元生成所述对准控制信号，以交换模式交换数据，其中所述突发类型是特定类型，并且位的种子地址组是某些值。

4. 发明申请

US20120225344A1 SEPARATOR FOR LITHIUM SECONDARY BATTERY AND LITHIUM SECONDARY BATTERY COMPRISING THE SAME 有权
标题翻译：用于锂二次电池的分离器和包含该电池的锂二次电池
公开(公告)号：US20120225344A1
公开(公告)日：2012-09-06
申请号：US13469866
申请日：2012-05-11
申请人： Ji-Jun Hong , In-Beom Hwang , Sung-Tae Ko , Kwang-Hyun Kim , Yoon-Jeong Heo
发明人： Ji-Jun Hong , In-Beom Hwang , Sung-Tae Ko , Kwang-Hyun Kim , Yoon-Jeong Heo
IPC分类号： H01M2/16
CPC分类号： H01M2/1653 , H01M10/052 , Y02E60/122
摘要： Disclosed is a separator for a lithium secondary battery and a lithium secondary battery comprising the same. The separator may include a thermoplastic polyolefin-based polymer porous sheet and an aramid-based non-woven fabric sheet stacked on at least one surface of the polyolefin-based polymer porous sheet, wherein the polyolefin-based polymer sheet and the aramid-based non-woven fabric sheet are adhered with an adhesive, and the adhesive loses an adhesive performance at 80° C. or more to separate the two sheets. The separator has a shut-down function and excellent high-temperature shape stability.
摘要翻译：公开了一种锂二次电池用隔膜和具备该二次电池的锂二次电池。隔板可以包括热塑性聚烯烃基聚合物多孔片和堆叠在聚烯烃基聚合物多孔片的至少一个表面上的芳族聚酰胺类非织造布片，其中聚烯烃基聚合物片和芳族聚酰胺类非织造布用粘合剂粘合编织织物片，并且粘合剂在80℃以上失去粘合性能以分离两片。分离器具有关闭功能和优异的高温形状稳定性。

5. 发明授权

US08225032B2 Circuit and method for generating data input buffer control signal 有权
标题翻译：用于产生数据输入缓冲器控制信号的电路和方法
公开(公告)号：US08225032B2
公开(公告)日：2012-07-17
申请号：US12490412
申请日：2009-06-24
申请人： Kwang-Hyun Kim
发明人： Kwang-Hyun Kim
IPC分类号： G06F13/00
CPC分类号： G11C7/1078 , G11C7/1066 , G11C7/1084 , G11C7/22 , G11C11/4076 , G11C11/4093 , G11C2207/2272
摘要： A data input buffer control signal generating device is capable of preventing unnecessary operation and current consumption of blocks and thus stabilizing an internal operation of DRAM by generating a control signal which controls an enabling timing of a data input buffer not to be conflicted with an output data. The data input buffer control signal generating device includes a write-related control unit configured to generate a data input buffer reference signal generated on the basis of a write latency by a write command, a read-related control unit configured to replicate a delay through a data output path, delay an end command for a data output termination and generate a delayed end command, wherein the end command is generated by a read command, and an output unit configured to output a data input buffer control signal by combining the data input buffer reference signal and the output of the delayed end command.
摘要翻译：数据输入缓冲器控制信号发生装置能够防止块的不必要的操作和电流消耗，从而通过产生控制信号来稳定DRAM的内部操作，该控制信号控制数据输入缓冲器的使能定时不与输出数据冲突。数据输入缓冲器控制信号产生装置包括：写入相关控制单元，被配置为生成基于写入命令的写入等待时间生成的数据输入缓冲器参考信号;读取相关控制单元，被配置为通过数据输出路径，延迟用于数据输出终止的结束命令，并生成延迟结束命令，其中结束命令由读取命令产生，以及输出单元，被配置为通过组合数据输入缓冲器来输出数据输入缓冲器控制信号参考信号和延迟结束命令的输出。

6. 发明授权

US07948592B2 Display device for increasing viewing angle 有权
标题翻译：用于增加视角的显示装置
公开(公告)号：US07948592B2
公开(公告)日：2011-05-24
申请号：US12469361
申请日：2009-05-20
申请人： Hee-Wook Do , Ki-Chul Shin , Seung-Hee Lee , Sung-Min Kang , Kwang-Hyun Kim , Ji-Hoon Kim , Sang-Jae Kim
发明人： Hee-Wook Do , Ki-Chul Shin , Seung-Hee Lee , Sung-Min Kang , Kwang-Hyun Kim , Ji-Hoon Kim , Sang-Jae Kim
IPC分类号： G02F1/1335
CPC分类号： G02F1/1393 , G02F1/13363 , G02F2413/03 , G02F2413/06 , G02F2413/08 , G02F2413/11
摘要： A display device includes a display panel, a first optical unit, and a second optical unit. The display panel includes a first substrate, a second substrate, and a liquid crystal layer disposed between the first substrate and the second substrate. The liquid crystal layer is operated in a vertical alignment mode. The first optical unit includes a C-plate and a first polarization plate having a first absorption axis. The second optical unit includes a positive A-plate, a negative A-plate, and a second polarization plate having a second absorption axis substantially perpendicular to the first absorption axis. The positive A-plate and the negative A-plate may gather dispersed polarization states of a colored light.
摘要翻译：显示装置包括显示面板，第一光学单元和第二光学单元。显示面板包括第一基板，第二基板和设置在第一基板和第二基板之间的液晶层。液晶层以垂直对准模式操作。第一光学单元包括C板和具有第一吸收轴的第一偏振板。第二光学单元包括正A板，负A板和具有基本上垂直于第一吸收轴的第二吸收轴的第二偏振板。正A板和负A板可能会聚集彩色光的分散极化状态。

7. 发明申请

US20110043730A1 DISPLAY APPARATUS PROVIDING SIDE VIEW LUMINANCE ENHANCEMENT 有权
标题翻译：显示设备提供侧视图亮度增强
公开(公告)号：US20110043730A1
公开(公告)日：2011-02-24
申请号：US12726056
申请日：2010-03-17
申请人： Hee-Wook DO , Ki-Chul Shin , Kwang-Hyun Kim , Ji-Hoon Kim
发明人： Hee-Wook DO , Ki-Chul Shin , Kwang-Hyun Kim , Ji-Hoon Kim
IPC分类号： G02F1/1335 , G02F1/13363
CPC分类号： G02F1/13362 , G02F1/13363 , G02F1/1393
摘要： A flat panel display device is provided with an increased viewing angle having good dark versus light imaging contrast. The display device includes a display panel, a first optical unit, and a second optical unit. The display panel includes a liquid crystal layer that is driven in a vertical alignment mode. The first optical unit includes a negative C-plate and a first polarizer having a first absorption axis. The second optical unit includes a biaxial compensation plate having a refractive indices coefficient, (nx−nz)/(nx−ny) of more than 0.45 and less than 0.55, and a second polarizer having a second absorption axis crossing the first absorption axis. The biaxial compensation plate has a refractive indices relationship of nx>nz>ny such that dispersion of polarization states of colored light rays passed through the C-plate and the liquid crystal layer may be minimized and gathered about an extinction point, thereby improving contrast at side viewing angles.
摘要翻译：平板显示装置具有增强的视角，具有良好的暗对比光成像对比度。显示装置包括显示面板，第一光学单元和第二光学单元。显示面板包括以垂直对准模式驱动的液晶层。第一光学单元包括负C板和具有第一吸收轴的第一偏振器。第二光学单元包括折射率系数（nx-nz）/（nx-ny）大于0.45且小于0.55的双轴补偿板，以及具有与第一吸收轴交叉的第二吸收轴的第二偏振器。双轴补偿板的折射率关系为nx> nz> ny，使得通过C板和液晶层的有色光的偏振态的分散可以最小化并聚集在消光点附近，从而改善了对比度侧视角。

8. 发明申请

US20100245752A1 LIQUID CRYSTAL DISPLAY 审中-公开
标题翻译：液晶显示器
公开(公告)号：US20100245752A1
公开(公告)日：2010-09-30
申请号：US12794338
申请日：2010-06-04
申请人： Sung-Hwan Hong , Myeong-Ha Kye , Kwang-Hyun Kim
发明人： Sung-Hwan Hong , Myeong-Ha Kye , Kwang-Hyun Kim
IPC分类号： C09K19/02
CPC分类号： G02F1/1396 , G02F1/1362
摘要： A liquid crystal display (LCD) includes a first electrode, a second electrode facing the first electrode, and a liquid crystal layer interposed between the first and second electrodes and having a twisted nematic alignment of liquid crystals, wherein rotation viscosity of the liquid crystal layer is 50 mPas-80 mPas, a cell gap, namely, the thickness of the liquid crystal layer, is 2.5 μm-5.0 μm, a voltage difference between the first and second electrodes is 0.2V-8.0V, and a response time can be obtained from the expression 6.78+(rotation viscosity)×0.81+(cell gap)×0.7+(rotation viscosity)×(cell gap)×0.14. The liquid crystal display having the twisted nematic alignment of liquid crystals, has the pitch of the liquid crystal layer within the range of 10 μm to 70 μm, a cell gap, namely, the thickness of the liquid crystal layer, within the range of 3.0 μm to 4.5 μm, and a voltage difference between the first and second electrodes within the range of 0.2V to 6.0V.
摘要翻译：液晶显示器（LCD）包括第一电极，面对第一电极的第二电极和介于第一和第二电极之间并具有液晶的扭曲向列取向的液晶层，其中液晶层的旋转粘度 50mPas-80mPa·s，单元间隙即液晶层的厚度为2.5μm〜5.0μm，第一和第二电极之间的电压差为0.2V〜8.0V，响应时间为（旋转粘度）×0.81 +（细胞间隙）×0.7 +（旋转粘度）×（细胞间隙）×0.14得到。具有液晶的扭曲向列取向的液晶显示器的液晶层的间距在10μm至70μm的范围内，单元间隙即液晶层的厚度在3.0的范围内 μm至4.5μm，第一和第二电极之间的电压差在0.2V至6.0V的范围内。

9. 发明申请

US20100008166A1 CIRCUIT AND METHOD FOR CONTROLLING LOADING OF WRITE DATA IN SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：用于控制半导体存储器件中写入数据的加载的电路和方法
公开(公告)号：US20100008166A1
公开(公告)日：2010-01-14
申请号：US12344687
申请日：2008-12-29
申请人： Sang-Hui Kim , Kwang-Hyun Kim
发明人： Sang-Hui Kim , Kwang-Hyun Kim
IPC分类号： G11C7/00
CPC分类号： G11C7/1027 , G11C7/02 , G11C7/1048 , G11C7/1078 , G11C11/4096
摘要： A circuit for controlling the loading of write data in a semiconductor memory device includes a global bus; a data block configured to selectively load data of a predetermined first burst length or data of a second burst length, which is a half of the first burst length, for writing on the global bus in response to a control signal; and a memory bank configured to write the data of the first burst length or the data of the second burst length.
摘要翻译：用于控制半导体存储器件中写入数据的加载的电路包括全局总线; 数据块，被配置为响应于控制信号选择性地加载预定的第一突发长度的数据或者是第一突发长度的一半的第二突发长度的数据写入全局总线上; 以及存储体，被配置为写入第一突发长度的数据或第二突发长度的数据。

10. 发明申请

US20080159050A1 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US20080159050A1
公开(公告)日：2008-07-03
申请号：US11819822
申请日：2007-06-29
申请人： Kwang-Hyun Kim
发明人： Kwang-Hyun Kim
IPC分类号： G11C8/00
CPC分类号： G11C7/1006 , G11C7/1012 , G11C11/4093 , G11C11/4097 , G11C2207/002
摘要： A semiconductor memory device includes data transmission devices for transmit data in synchronization with each other. The semiconductor memory device includes a plurality of data transferring unit, a first control unit, a multiplexing unit, and a second control unit. The plurality of data transferring unit transfers data to a plurality of global lines. The first control unit controls the plurality of data transferring unit in response to a column select signal to select a column of a memory cell. The multiplexing unit multiplexes the data transferred to the plurality of global lines. The second control unit controls the multiplexing unit, wherein the second control unit synchronizes the column select signal with a column address signal having a column address information of the memory cell.
摘要翻译：半导体存储器件包括用于彼此同步地发送数据的数据传输装置。半导体存储器件包括多个数据传送单元，第一控制单元，复用单元和第二控制单元。多个数据传送单元将数据传送到多条全局线路。第一控制单元响应于列选择信号控制多个数据传送单元以选择存储单元的列。复用单元复用传输到多条全局线路的数据。第二控制单元控制复用单元，其中第二控制单元将列选择信号与具有存储单元的列地址信息的列地址信号同步。

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