专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20110216606A1 DATA OUTPUT CIRCUIT OF SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：半导体存储器件的数据输出电路
公开(公告)号：US20110216606A1
公开(公告)日：2011-09-08
申请号：US12751425
申请日：2010-03-31
申请人： Kwang-Hyun KIM , Kang-Youl Lee
发明人： Kwang-Hyun KIM , Kang-Youl Lee
IPC分类号： G11C7/10 , G11C7/00
CPC分类号： G11C7/00 , G11C7/10
摘要： A data output circuit of a semiconductor memory device includes a pipe latch unit configured to store input parallel data and align the stored data in response to a plurality of alignment control signals to output serial output data, and an alignment control signal generating unit configured to generate the plurality of alignment control signals in response to a burst-type information and a seed address group, wherein the alignment control signal generating unit generates the alignment control signals to swap data in a swap mode where the burst-type is a certain type and bits of the seed address group are certain values.
摘要翻译：一种半导体存储器件的数据输出电路，包括配置为存储输入并行数据并响应于多个对准控制信号对准存储的数据以输出串行输出数据的管锁存单元，以及对准控制信号生成单元，所述多个对准控制信号响应于突发类型信息和种子地址组，其中所述对准控制信号生成单元生成所述对准控制信号，以交换模式交换数据，其中所述突发类型是特定类型，并且位的种子地址组是某些值。

2. 发明授权

US08305819B2 Data output circuit of semiconductor memory device 有权
标题翻译：半导体存储器件的数据输出电路
公开(公告)号：US08305819B2
公开(公告)日：2012-11-06
申请号：US12751425
申请日：2010-03-31
申请人： Kwang-Hyun Kim , Kang-Youl Lee
发明人： Kwang-Hyun Kim , Kang-Youl Lee
IPC分类号： G11C7/10
CPC分类号： G11C7/00 , G11C7/10
摘要： A data output circuit of a semiconductor memory device includes a pipe latch unit configured to store input parallel data and align the stored data in response to a plurality of alignment control signals to output serial output data, and an alignment control signal generating unit configured to generate the plurality of alignment control signals in response to a burst-type information and a seed address group, wherein the alignment control signal generating unit generates the alignment control signals to swap data in a swap mode where the burst-type is a certain type and bits of the seed address group are certain values.
摘要翻译：一种半导体存储器件的数据输出电路，包括配置为存储输入并行数据并响应于多个对准控制信号对准存储的数据以输出串行输出数据的管锁存单元，以及对准控制信号生成单元，所述多个对准控制信号响应于突发类型信息和种子地址组，其中所述对准控制信号生成单元生成所述对准控制信号，以交换模式交换数据，其中所述突发类型是特定类型，并且位的种子地址组是某些值。

3. 发明授权

US08259519B2 Synchronous semiconductor memory device 有权
标题翻译：同步半导体存储器件
公开(公告)号：US08259519B2
公开(公告)日：2012-09-04
申请号：US12914541
申请日：2010-10-28
申请人： Kang-Youl Lee
发明人： Kang-Youl Lee
IPC分类号： G11C7/00
CPC分类号： G11C11/4076 , G11C7/1006 , G11C7/1078 , G11C7/1084 , G11C7/109 , G11C7/1093 , G11C7/1096 , G11C7/22 , G11C11/4093
摘要： A synchronous semiconductor memory device includes a data alignment reference pulse generation unit configured to generate a data alignment reference pulse in response to a data strobe signal, a data alignment suspension signal generation unit configured to generate a data alignment suspension signal in response to the data alignment reference pulse, a data strobe termination signal, and a write pulse, and a data alignment unit configured to align input data in response to the data alignment reference pulse and stop aligning the input data in response to the data alignment suspension signal.
摘要翻译：同步半导体存储器件包括：数据对准基准脉冲产生单元，被配置为响应于数据选通信号产生数据对准参考脉冲;数据对准暂停信号生成单元，被配置为响应于数据对准生成数据对准悬置信号参考脉冲，数据选通终止信号和写入脉冲，以及数据对准单元，被配置为响应于数据对准参考脉冲对准输入数据，并响应于数据对准暂停信号停止对准输入数据。

4. 发明授权

US06741117B2 Antifuse circuit 有权
标题翻译：防腐电路
公开(公告)号：US06741117B2
公开(公告)日：2004-05-25
申请号：US10331292
申请日：2002-12-30
申请人： Kang-Youl Lee
发明人： Kang-Youl Lee
IPC分类号： H01H3776
CPC分类号： G11C17/18
摘要： An antifuse circuit serves to generate an antifuse enable signal for use in repairing a defected memory cell in a semiconductor device. The inventive antifuse includes: an antifuse unit employing an antifuse, wherein the antifuse is controlled as being shorted or insulated according to a repair program; an antifuse precharge unit for precharging the antifuse by using a predetermined voltage level in response to a power-up signal, wherein the predetermined voltage level is lower than that of an external voltage source; and an output latch unit driven by the predetermined voltage level for latching a antifuse voltage level appearing on the antifuse and generating the antifuse enable signal corresponding to the antifuse voltage level.
摘要翻译：反熔丝电路用于产生用于修复半导体器件中的缺陷存储单元的反熔断使能信号。本发明的反熔丝包括：使用反熔丝的反熔丝单元，其中根据维修程序将反熔丝控制为短路或绝缘; 反熔丝预充电单元，用于响应于上电信号使用预定电压电平来预充电反熔丝，其中所述预定电压电平低于外部电压源的预定电压电平; 以及由预定电压电平驱动的输出锁存单元，用于锁存出现在反熔丝上的反熔丝电压电平，并产生对应于反熔丝电压电平的反熔丝使能信号。

5. 发明授权

US07092306B2 Semiconductor device capable of adjusting operation timing using antifuse 失效
标题翻译：能够使用反熔丝来调整操作定时的半导体装置
公开(公告)号：US07092306B2
公开(公告)日：2006-08-15
申请号：US10732639
申请日：2003-12-10
申请人： Kang-Youl Lee
发明人： Kang-Youl Lee
IPC分类号： G11C11/06
CPC分类号： G11C29/028 , G11C11/401 , G11C29/50 , G11C29/50012 , H01L23/5252 , H01L2924/0002 , H03K5/135 , H03K2005/00071 , H01L2924/00
摘要： A semiconductor device controls an error of the AC parameter caused by a processing variation without reproduction of the semiconductor device, thereby reducing the new design and developing time. The semiconductor device includes an antifuse unit having a plurality of programmable antifuses and producing digital coding signals by programming the antifuses in a test mode. The semiconductor device also includes a timing adjustor for adjusting an output time of an input signal by using the digital coding signals. The timing adjustor includes a plurality of capacitors for producing different delay times of the input signal, and a latch circuit for latching a delayed input signal in response to a data strobe signal.
摘要翻译：半导体器件控制由加工变化引起的AC参数的误差，而不会重现半导体器件，从而减少新的设计和开发时间。半导体器件包括具有多个可编程反熔丝的反熔丝单元，并且通过在测试模式中编程反熔丝来产生数字编码信号。半导体器件还包括用于通过使用数字编码信号来调节输入信号的输出时间的定时调节器。定时调整器包括用于产生输入信号的不同延迟时间的多个电容器，以及用于响应数据选通信号来锁存延迟的输入信号的锁存电路。

6. 发明授权

US07020029B2 Semiconductor memory device for preventing skew and timing error of output data 有权
标题翻译：用于防止输出数据的偏移和定时误差的半导体存储器件
公开(公告)号：US07020029B2
公开(公告)日：2006-03-28
申请号：US10745738
申请日：2003-12-23
申请人： Kang-Youl Lee
发明人： Kang-Youl Lee
IPC分类号： G11C7/00
CPC分类号： G11C5/063
摘要： A semiconductor memory device includes at least memory cell block which has a plurality of memory cells and outputs a plurality of data signals in response to a read command signal; a data latching unit for latching and outputting the plurality of data signals in response to a data output control signal generated in response to the read command signal; a data selection unit for selecting a data output mode from the plurality of data output modes in response to a data selection signal and for outputting data corresponding to the selected data output mode; and a data output control unit for outputting a data selection signal to the data selection unit in response to the data output control signal.
摘要翻译：半导体存储器件至少包括具有多个存储器单元的存储器单元块，并且响应于读取命令信号而输出多个数据信号; 数据锁存单元，用于响应于读取的命令信号产生的数据输出控制信号来锁存和输出多个数据信号; 数据选择单元，用于响应于数据选择信号从多个数据输出模式中选择数据输出模式，并输出与所选数据输出模式对应的数据; 以及数据输出控制单元，用于响应于数据输出控制信号将数据选择信号输出到数据选择单元。

7. 发明申请

US20050094442A1 Semiconductor memory device for preventing skew and timing error of output data 有权
标题翻译：用于防止输出数据的偏移和定时误差的半导体存储器件
公开(公告)号：US20050094442A1
公开(公告)日：2005-05-05
申请号：US10745738
申请日：2003-12-23
申请人： Kang-Youl Lee
发明人： Kang-Youl Lee
IPC分类号： G11C7/00 , G11C5/00 , G11C5/06
CPC分类号： G11C5/063
摘要： A semiconductor memory device includes at least memory cell block which has a plurality of memory cells and outputs a plurality of data signals in response to a read command signal; a data latching unit for latching and outputting the plurality of data signals in response to a data output control signal generated in response to the read command signal; a data selection unit for selecting a data output mode from the plurality of data output modes in response to a data selection signal and for outputting data corresponding to the selected data output mode; and a data output control unit for outputting a data selection signal to the data selection unit in response to the data output control signal.
摘要翻译：半导体存储器件至少包括具有多个存储器单元的存储器单元块，并且响应于读取命令信号而输出多个数据信号; 数据锁存单元，用于响应于读取的命令信号产生的数据输出控制信号来锁存和输出多个数据信号; 数据选择单元，用于响应于数据选择信号从多个数据输出模式中选择数据输出模式，并输出与所选数据输出模式对应的数据; 以及数据输出控制单元，用于响应于数据输出控制信号将数据选择信号输出到数据选择单元。

8. 发明授权

US08947959B2 Memory device and compressive test method for the same 有权
标题翻译：记忆体和压缩试验方法相同
公开(公告)号：US08947959B2
公开(公告)日：2015-02-03
申请号：US13206180
申请日：2011-08-09
申请人： Kang-Youl Lee
发明人： Kang-Youl Lee
IPC分类号： G11C7/00 , G11C29/00 , G11C29/40 , G11C29/28 , G11C29/26
CPC分类号： G11C29/40 , G11C29/28 , G11C2029/2602
摘要： A memory device includes a first bank, a second bank, a plurality of interface pads, and a data output unit configured to output compressed data of the first bank through at least one interface pad among the plurality of interface pads and subsequently output compressed data of the second bank through the one interface pad.
摘要翻译：存储器件包括第一存储体，第二存储体，多个接口焊盘和数据输出单元，其被配置为通过多个接口焊盘中的至少一个接口焊盘输出第一存储体的压缩数据，并随后输出压缩数据第二个银行通过一个界面垫。

9. 发明授权

US08559242B2 Data output circuit and method 失效
标题翻译：数据输出电路及方法
公开(公告)号：US08559242B2
公开(公告)日：2013-10-15
申请号：US13269492
申请日：2011-10-07
申请人： Kang-Youl Lee
发明人： Kang-Youl Lee
IPC分类号： G11C7/10
CPC分类号： G11C11/4097 , G11C7/1051 , G11C7/106 , G11C2207/107
摘要： A data output circuit includes a strobe signal controlling block configured to generate a first delayed strobe signal by delaying a first strobe signal by a certain delay amount, an input/output sense amplifying block configured to amplify first parallel data signals to generate second parallel data signals having the same number of bits as that of the first parallel data signals in response to the first strobe signal and the first delayed strobe signal, a storing block configured to latch the second parallel data signals in response to a second strobe signal and a second delayed strobe signal, and a parallel-to-serial converting block configured to sequentially output the second parallel data signals latched in the storing block, wherein the first strobe signal is used to generate a data signal that is outputted first among the second parallel data signals.
摘要翻译：数据输出电路包括选通信号控制模块，配置为通过将第一选通信号延迟一定的延迟量来产生第一延迟选通信号;输入/输出读出放大块，被配置为放大第一并行数据信号以产生第二并行数据信号响应于第一选通信号和第一延迟选通信号，具有与第一并行数据信号相同数量的位数;存储块，被配置为响应于第二选通信号和第二延迟选通信号而锁存第二并行数据信号选通信号和并行到串行转换块，被配置为顺序地输出锁存在存储块中的第二并行数据信号，其中第一选通信号用于产生在第二并行数据信号中首先输出的数据信号。

10. 发明申请

US20110291717A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20110291717A1
公开(公告)日：2011-12-01
申请号：US12839689
申请日：2010-07-20
申请人： Kang-Youl Lee
发明人： Kang-Youl Lee
IPC分类号： H03L7/06
CPC分类号： H03L7/07 , H03L7/0814
摘要： A semiconductor device includes a delay locked loop including a replica delay unit which is configured to delay a signal reflecting a delay amount of an output path of a signal, and a delay time compensator configured to compensate for a difference of a delay time between the replica delay unit and the output path by comparing an output signal of the replica delay unit and an output signal of the output path.
摘要翻译：一种半导体器件包括：延迟锁定环，包括复制延迟单元，其被配置为延迟反映信号的输出路径的延迟量的信号;以及延迟时间补偿器，被配置为补偿复制品之间的延迟时间的差异延迟单元和输出路径，通过比较复制延迟单元的输出信号和输出路径的输出信号。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式