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1. 发明授权

US07605623B2 Semiconductor memory apparatus with a delay locked loop circuit 有权
标题翻译：具有延迟锁定环路的半导体存储装置
公开(公告)号：US07605623B2
公开(公告)日：2009-10-20
申请号：US11824428
申请日：2007-06-29
申请人： Won-Joo Yun , Hyun-Woo Lee
发明人： Won-Joo Yun , Hyun-Woo Lee
IPC分类号： H03L7/06
CPC分类号： H03L7/0814 , H03L7/0818 , H03L7/087 , H03L7/095
摘要： A semiconductor memory apparatus includes a delay line configured to delay a reference clock, a first delay block configured to delay a feedback clock, a first phase comparator configured to compare the reference clock with an output of the first delay block, a second delay block configured to delay the reference clock, a second phase comparator configured to compare the feedback clock with an output of the second delay block, a delay controller configured to control a delay amount of the delay line based on comparison results from the first and second phase comparators, a delay model configured to delay an output of the delay line by a modeled delay time to generate the feedback clock, and a locking detector configured to control the delay controller based on comparison results from the first and second phase comparators.
摘要翻译：一种半导体存储装置，包括：延迟线，被配置为延迟参考时钟;第一延迟块，被配置为延迟反馈时钟;第一相位比较器，被配置为将参考时钟与第一延迟块的输出进行比较;第二延迟块，延迟参考时钟;第二相位比较器，被配置为将反馈时钟与第二延迟块的输出进行比较;延迟控制器，被配置为基于来自第一和第二相位比较器的比较结果来控制延迟线的延迟量，延迟模型，被配置为延迟延迟线的输出通过建模的延迟时间以产生反馈时钟;以及锁定检测器，被配置为基于来自第一和第二相位比较器的比较结果来控制延迟控制器。

2. 发明申请

US20090121784A1 POWER-DOWN MODE CONTROL APPARATUS AND DLL CIRCUIT HAVING THE SAME 有权
标题翻译：掉电模式控制装置和具有该模式的DLL电路
公开(公告)号：US20090121784A1
公开(公告)日：2009-05-14
申请号：US12175212
申请日：2008-07-17
申请人： Hyun-Woo Lee , Won-Joo Yun , Dong-Suk Shin
发明人： Hyun-Woo Lee , Won-Joo Yun , Dong-Suk Shin
IPC分类号： G05F1/10
CPC分类号： G11C7/02 , G11C5/143 , G11C5/144 , G11C7/22 , G11C7/222
摘要： A power-down mode control apparatus includes an internal power-down control block configured to receive a locking completion signal and to generate an internal power-down signal, which is toggled for a predetermined time; a noise check block configured to check occurrence/non-occurrence of noise on the basis of a phase detection signal and to generate a plurality of power-down selection signals in response to the locking completion signal and the internal power-down signal; and a power-down enter control block configured to generate a plurality of power-down enter signals, which instruct individual circuits to enter a power-down mode in response to a reference clock signal, the plurality of power-down selection signals, a power-down mode signal, and the internal power-down signal.
摘要翻译：断电模式控制装置包括内部掉电控制块，其被配置为接收锁定完成信号并产生切换预定时间的内部掉电信号; 噪声检查块，被配置为基于相位检测信号来检查噪声的发生/不发生，并且响应于锁定完成信号和内部掉电信号而产生多个掉电选择信号; 以及断电进入控制块，被配置为产生多个断电输入信号，其响应于参考时钟信号指示各个电路进入掉电模式，所述多个掉电选择信号，功率下降模式信号和内部掉电信号。

3. 发明申请

US20080054964A1 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US20080054964A1
公开(公告)日：2008-03-06
申请号：US11819783
申请日：2007-06-29
申请人： Hyun-Woo Lee , Won-Joo Yun
发明人： Hyun-Woo Lee , Won-Joo Yun
IPC分类号： G11C8/00 , H03L7/06
CPC分类号： G11C7/1072 , G11C7/222 , H03L7/07 , H03L7/0814 , H03L7/0818
摘要： A semiconductor memory device includes a delay locked loop for correcting a duty cycle rate of a delay locked clock signal. The semiconductor memory device includes a delay locked circuit, a duty cycle correction circuit, and a clock synchronization circuit. The delay locked circuit outputs a delay locked clock by delaying a system clock by a predetermined time. The duty cycle correction circuit outputs a first clock by correcting a duty cycle of the delay locked clock, wherein the proportion of high to low level periods of the delay locked clock is controlled according to a time difference between a second edge of the first clock and that of a second clock derived from the first clock. The clock synchronization circuit synchronizes a first edge of the first clock with that of the second clock.
摘要翻译：半导体存储器件包括用于校正延迟锁定时钟信号的占空比的延迟锁定环路。半导体存储器件包括延迟锁定电路，占空比校正电路和时钟同步电路。延迟锁定电路通过将系统时钟延迟预定时间来输出延迟锁定时钟。占空比校正电路通过校正延迟锁定时钟的占空比来输出第一时钟，其中延迟锁定时钟的高电平到低电平周期的比例根据第一时钟的第二边沿和来自第一时钟的第二时钟的信号。时钟同步电路将第一时钟的第一边沿与第二时钟的第一边沿同步。

4. 发明授权

US07764096B2 DLL circuit and method of controlling the same 有权
标题翻译： DLL电路及其控制方法
公开(公告)号：US07764096B2
公开(公告)日：2010-07-27
申请号：US12173728
申请日：2008-07-15
申请人： Hyun-Woo Lee , Won-Joo Yun
发明人： Hyun-Woo Lee , Won-Joo Yun
IPC分类号： H03L7/06
CPC分类号： H03L7/07 , H03L7/0812 , H03L7/0814
摘要： A delay locked loop (DLL) circuit includes a clock signal dividing unit that can divide a reference clock signal by a predetermined division ratio and generate a division clock signal, a feedback loop that can perform a delay locked operation on the division clock signal and generate a delay clock signal, a half period delay unit that can delay the delay clock signal by a half period of the reference clock signal and generate a half period delay clock signal, and an operation unit that can combine the delay clock signal and the half period delay clock signal and generate an output clock signal.
摘要翻译：延迟锁定环（DLL）电路包括时钟信号划分单元，其可以将预定分频比除以参考时钟信号并产生除法时钟信号，该反馈环可以对分频时钟信号执行延迟锁定操作并产生延迟时钟信号，半周期延迟单元，其可以将所述延迟时钟信号延迟所述基准时钟信号的半周期，并生成半周期延迟时钟信号;以及操作单元，其可以将所述延迟时钟信号和所述半周期延迟时钟信号并产生输出时钟信号。

5. 发明授权

US07633324B2 Data output strobe signal generating circuit and semiconductor memory apparatus having the same 有权
标题翻译：数据输出选通信号发生电路及其半导体存储装置
公开(公告)号：US07633324B2
公开(公告)日：2009-12-15
申请号：US11878074
申请日：2007-07-20
申请人： Won-Joo Yun , Hyun-Woo Lee
发明人： Won-Joo Yun , Hyun-Woo Lee
IPC分类号： H03L7/00
CPC分类号： H03L7/0812 , H03K5/1565 , H03K2005/00058
摘要： A data output strobe signal generating circuit includes a duty cycle correcting unit that corrects the duty ratio of an input clock in response to a control signal to generate a corrected clock. A data output strobe signal generating unit receives the corrected clock and generates a data output strobe signal. A duty cycle control unit receives the data output strobe signal and outputs the control signal.
摘要翻译：数据输出选通信号产生电路包括占空比校正单元，其根据控制信号校正输入时钟的占空比，以产生校正时钟。数据输出选通信号发生单元接收校正的时钟并产生数据输出选通信号。占空比控制单元接收数据输出选通信号并输出控制信号。

6. 发明申请

US20090295446A1 DUTY CYCLE CORRECTING CIRCUIT AND METHOD OF CORRECTING A DUTY CYCLE 有权
标题翻译：占空比校正电路和校正周期的方法
公开(公告)号：US20090295446A1
公开(公告)日：2009-12-03
申请号：US12345480
申请日：2008-12-29
申请人： Won-Joo Yun , Hyun-Woo Lee
发明人： Won-Joo Yun , Hyun-Woo Lee
IPC分类号： H03K3/017
CPC分类号： H03K5/1565
摘要： A duty cycle correcting circuit includes a duty ratio control unit configured to alternately change logical values of a plurality of bits of a pull-up control signal and a plurality of bits of a pull-down control signal in response to a duty ratio detection signal, a duty ratio correcting unit configured to adjust driving abilities of a first driver and a second driver in response to the plurality of bits of the pull-up control signal and the plurality of bits of the pull-down control signal to output a correction clock signal, and a duty ratio detecting unit configured to detect a duty ratio of the correction clock to generate the duty ratio detection signal.
摘要翻译：占空比校正电路包括占空比控制单元，其被配置为响应于占空比检测信号交替地改变上拉控制信号的多个比特和下拉控制信号的多个比特的逻辑值，占空比校正单元，被配置为响应于所述上拉控制信号的多个比特和所述下拉控制信号的多个比特来调整第一驱动器和第二驱动器的驱动能力，以输出校正时钟信号以及占空比检测单元，被配置为检测校正时钟的占空比以产生占空比检测信号。

7. 发明授权

US07535270B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07535270B2
公开(公告)日：2009-05-19
申请号：US11819783
申请日：2007-06-29
申请人： Hyun-Woo Lee , Won-Joo Yun
发明人： Hyun-Woo Lee , Won-Joo Yun
IPC分类号： H03L7/06
CPC分类号： G11C7/1072 , G11C7/222 , H03L7/07 , H03L7/0814 , H03L7/0818
摘要： A semiconductor memory device includes a delay locked loop for correcting a duty cycle rate of a delay locked clock signal. The semiconductor memory device includes a delay locked circuit, a duty cycle correction circuit, and a clock synchronization circuit. The delay locked circuit outputs a delay locked clock by delaying a system clock by a predetermined time. The duty cycle correction circuit outputs a first clock by correcting a duty cycle of the delay locked clock, wherein the proportion of high to low level periods of the delay locked clock is controlled according to a time difference between a second edge of the first clock and that of a second clock derived from the first clock. The clock synchronization circuit synchronizes a first edge of the first clock with that of the second clock.
摘要翻译：半导体存储器件包括用于校正延迟锁定时钟信号的占空比的延迟锁定环路。半导体存储器件包括延迟锁定电路，占空比校正电路和时钟同步电路。延迟锁定电路通过将系统时钟延迟预定时间来输出延迟锁定时钟。占空比校正电路通过校正延迟锁定时钟的占空比来输出第一时钟，其中延迟锁定时钟的高电平到低电平周期的比例根据第一时钟的第二边沿和来自第一时钟的第二时钟的信号。时钟同步电路将第一时钟的第一边沿与第二时钟的第一边沿同步。

8. 发明授权

US07761757B2 Apparatus and method of setting test mode in semiconductor integrated circuit 有权
标题翻译：设置半导体集成电路测试模式的方法和设备
公开(公告)号：US07761757B2
公开(公告)日：2010-07-20
申请号：US12013866
申请日：2008-01-14
申请人： Won-Joo Yun , Hyun-Woo Lee , Dong-Suk Shin
发明人： Won-Joo Yun , Hyun-Woo Lee , Dong-Suk Shin
IPC分类号： G01R31/28
CPC分类号： G11C29/46 , G11C29/14 , G11C2029/0407 , Y10T307/747 , Y10T307/826 , Y10T307/858 , Y10T307/977
摘要： An apparatus for setting a test mode in a semiconductor integrated circuit includes a test mode control block that generates a coding control signal according to whether or not a control fuse is cut, and a test mode coding block that sets default values of a multi-bit test code in response to the coding control signal.
摘要翻译：一种用于在半导体集成电路中设置测试模式的装置包括：测试模式控制块，其根据是否切断控制熔丝产生编码控制信号;以及测试模式编码块，其设置多位的默认值响应于编码控制信号的测试码。

9. 发明授权

US07733147B2 Delay circuit of delay locked loop having single and dual delay lines and control method of the same 有权
标题翻译：具有单延迟线和双延迟线的延迟锁定环路的延迟电路及其控制方法
公开(公告)号：US07733147B2
公开(公告)日：2010-06-08
申请号：US12172887
申请日：2008-07-14
申请人： Hyun-Woo Lee , Won-Joo Yun
发明人： Hyun-Woo Lee , Won-Joo Yun
IPC分类号： H03H11/26
CPC分类号： H03L7/0814 , H03K5/133 , H03K2005/00052 , H03K2005/00058
摘要： A delay circuit in a delay locked loop includes a first delay circuit unit for delaying an input signal using a single delay line in response to first control signals and then outputting a first delay signal and a second delay signal, and a second delay circuit unit for delaying the first delay signal and the second delay signal by delay time, which is correspondent to second control signals and third control signals, using a dual delay line and then outputting a third delay signal and a fourth delay signal.
摘要翻译：延迟锁定环路中的延迟电路包括：第一延迟电路单元，用于响应于第一控制信号使用单个延迟线延迟输入信号，然后输出第一延迟信号和第二延迟信号;以及第二延迟电路单元，使用双延迟线延迟与第二控制信号和第三控制信号对应的延迟时间的第一延迟信号和第二延迟信号，然后输出第三延迟信号和第四延迟信号。

10. 发明授权

US07557627B2 Semiconductor memory device for generating a delay locked clock in early stage 有权
标题翻译：用于在早期产生延迟锁定时钟的半导体存储器件
公开(公告)号：US07557627B2
公开(公告)日：2009-07-07
申请号：US11715783
申请日：2007-03-08
申请人： Hyun-Woo Lee , Won-Joo Yun
发明人： Hyun-Woo Lee , Won-Joo Yun
IPC分类号： H03L7/06
CPC分类号： G11C8/18 , G11C7/22 , G11C7/222 , H03L7/07 , H03L7/0814 , H03L7/095
摘要： A semiconductor memory apparatus includes a first delay locked loop configured to delay a system clock by a predetermined time to thereby generate a first delay locked clock synchronizing a data output timing with the system clock, a second delay locked loop configured to delay an inverse signal of the system clock by a predetermined time to thereby generate a second delay locked clock synchronizing the data output timing with the system clock, and a clock selection block configured to select one of the first and second delay locked clocks to thereby output as a reference clock for data output.
摘要翻译：半导体存储装置包括第一延迟锁定环，其被配置为将系统时钟延迟预定时间，从而产生使数据输出定时与系统时钟同步的第一延迟锁定时钟;第二延迟锁定环，被配置为延迟系统时钟的反相信号系统时钟预定时间，从而产生将数据输出定时与系统时钟同步的第二延迟锁定时钟，以及配置为选择第一和第二延迟锁定时钟之一的时钟选择块，从而作为参考时钟输出数据输出。

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