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1. 发明申请

US20060006447A1 Semiconductor devices having a metal-insulator-metal capacitor and methods of forming the same 有权
公开(公告)号：US20060006447A1
公开(公告)日：2006-01-12
申请号：US11180954
申请日：2005-07-12
申请人： Hyun-Ho Kim , Heung-Jin Joo , Ki-Nam Kim
发明人： Hyun-Ho Kim , Heung-Jin Joo , Ki-Nam Kim
IPC分类号： H01L27/108
CPC分类号： H01L28/75 , H01L27/10852 , H01L27/11502 , H01L27/11507 , H01L28/55 , H01L28/65 , H01L28/91
摘要： A semiconductor device having an MIM capacitor and a method of forming the same are provided. A lower electrode includes a plate electrode and a sidewall electrode. The plate electrode is formed by a patterning process preferably including a plasma anisotropic etching. The sidewall electrode is formed like a spacer on an inner sidewall of an opening exposing the plate electrode by a plasma entire surface anisotropic etching.

2. 发明授权

US07495311B2 Semiconductor devices having a metal-insulator-metal capacitor and methods of forming the same 有权
标题翻译：具有金属 - 绝缘体 - 金属电容器的半导体器件及其形成方法
公开(公告)号：US07495311B2
公开(公告)日：2009-02-24
申请号：US11180954
申请日：2005-07-12
申请人： Hyun-Ho Kim , Heung-Jin Joo , Ki-Nam Kim
发明人： Hyun-Ho Kim , Heung-Jin Joo , Ki-Nam Kim
IPC分类号： H01L29/94
CPC分类号： H01L28/75 , H01L27/10852 , H01L27/11502 , H01L27/11507 , H01L28/55 , H01L28/65 , H01L28/91
摘要： A semiconductor device having an MIM capacitor and a method of forming the same are provided. A lower electrode includes a plate electrode and a sidewall electrode. The plate electrode is formed by a patterning process preferably including a plasma anisotropic etching. The sidewall electrode is formed like a spacer on an inner sidewall of an opening exposing the plate electrode by a plasma entire surface anisotropic etching.
摘要翻译：提供了具有MIM电容器的半导体器件及其形成方法。下电极包括平板电极和侧壁电极。板电极通过优选包括等离子体各向异性蚀刻的图案化工艺形成。侧壁电极通过等离子体整体表面各向异性蚀刻在露出板电极的开口的内侧壁上形成为间隔件。

3. 发明申请

US20080111171A1 Node structures under capacitor in ferroelectric random access memory device and methods of forming the same 审中-公开
标题翻译：铁电随机存取存储器件中电容器下的节点结构及其形成方法
公开(公告)号：US20080111171A1
公开(公告)日：2008-05-15
申请号：US11811931
申请日：2007-06-12
申请人： Heung-Jin Joo , Yoon-Jong Song , Ki-Nam Kim
发明人： Heung-Jin Joo , Yoon-Jong Song , Ki-Nam Kim
IPC分类号： H01L29/94 , H01L21/02
CPC分类号： H01L27/11502 , H01L27/11507 , H01L28/55
摘要： In a node structure under a capacitor in a ferroelectric random access memory device and a method of forming the same, top surfaces of the node structures are disposed at substantially the same level as a top surface of an interlayer insulating layer surrounding the node structures, and thus crystal growth of a ferroelectric in the capacitor can be stabilized. To this end, a node insulating pattern is formed on a semiconductor substrate. A node defining pattern surrounding the node insulating pattern is disposed under the node insulating pattern. A node conductive pattern is disposed between the node defining pattern and the node insulating pattern.
摘要翻译：在铁电随机存取存储器件中的电容器下的节点结构及其形成方法中，节点结构的顶表面设置在与节点结构周围的层间绝缘层的顶表面基本相同的水平处，并且因此可以使电容器中的铁电体的晶体生长稳定。为此，在半导体衬底上形成节点绝缘图案。定义节点绝缘图案周围的节点的节点设置在节点绝缘图案之下。节点导电图案设置在节点限定图案和节点绝缘图案之间。

4. 发明授权

US06911362B2 Methods for forming electronic devices including capacitor structures 失效
标题翻译：用于形成包括电容器结构的电子器件的方法
公开(公告)号：US06911362B2
公开(公告)日：2005-06-28
申请号：US10635195
申请日：2003-08-06
申请人： Ki-Nam Kim , Yoon-Jong Song , Heung-Jin Joo
发明人： Ki-Nam Kim , Yoon-Jong Song , Heung-Jin Joo
IPC分类号： H01L27/105 , H01L21/8246 , H01L27/115 , H01L21/8242
CPC分类号： H01L27/11502 , H01L27/11507
摘要： Methods for forming an electronic device can include forming a capacitor structure on a portion of a substrate with the capacitor structure including a first electrode on the substrate, a capacitor dielectric on the first electrode, a second electrode on the dielectric, and a hard mask on the second electrode. More particularly, the capacitor dielectric can be between the first and second electrodes, the first electrode and the capacitor dielectric can be between the second electrode and the substrate, and the first and second electrodes and the capacitor dielectric can be between the hard mask and the substrate. An interlayer dielectric layer can be formed on the hard mask and on portions of the substrate surrounding the capacitor structure, and portions of the interlayer dielectric layer can be removed to expose the hard mask while maintaining portions of the interlayer dielectric layer on portions of the substrate surrounding the capacitor structure. The hard mask can then be removed thereby exposing portions of the second electrode while maintaining the portions of the interlayer dielectric layer on portions of the substrate surrounding the capacitor.
摘要翻译：用于形成电子器件的方法可以包括在衬底的一部分上形成电容器结构，其中电容器结构包括在衬底上的第一电极，第一电极上的电容器电介质，电介质上的第二电极，第二电极。更具体地，电容器电介质可以在第一和第二电极之间，第一电极和电容器电介质可以在第二电极和衬底之间，并且第一和第二电极和电容器电介质可以在硬掩模和第二电极之间基质。可以在硬掩模和围绕电容器结构的基板的部分上形成层间电介质层，并且可以去除层间介电层的部分以暴露硬掩模，同时将层间电介质层的部分保持在基板的部分上围绕电容器结构。然后可以去除硬掩模，从而暴露第二电极的部分，同时保持层间电介质层的部分在包围电容器的基板的部分上。

5. 发明申请

US20070189056A1 STACKED FERROELECTRIC MEMORY DEVICES, METHODS OF MANUFACTURING THE SAME, FERROELECTRIC MEMORY CIRCUITS AND METHODS OF DRIVING THE SAME 失效
标题翻译：堆叠式电磁存储器件，其制造方法，电磁存储器电路及其驱动方法
公开(公告)号：US20070189056A1
公开(公告)日：2007-08-16
申请号：US11675007
申请日：2007-02-14
申请人： Heung-Jin Joo , Byung-Gil Jeon , Byoung-Jae Bae , Ki-Nam Kim
发明人： Heung-Jin Joo , Byung-Gil Jeon , Byoung-Jae Bae , Ki-Nam Kim
IPC分类号： G11C11/22
CPC分类号： G11C11/22 , G11C11/221 , G11C11/223
摘要： A stacked ferroelectric memory device has selection transistors including a first gate structure, a first impurity region, a second impurity region, a first insulating interlayer covering the selection transistors, bit line structures electrically connected to the first impurity regions, a second insulating interlayer covering the bit line structures, doped single crystalline silicon plugs formed through the first and the second insulating interlayers, each of which contacts the second impurity region and has a height greater than that of the bit line structures, active patterns disposed on the plugs and the second insulating interlayer, each of which contacts the plugs, and ferroelectric transistors disposed on the active patterns, each of which has a second gate structure including a ferroelectric layer pattern and a conductive pattern, a third impurity region and a fourth impurity region. The ferroelectric memory device performs a random access operation and has a high degree of integration.
摘要翻译：堆叠的铁电存储器件具有包括第一栅极结构，第一杂质区，第二杂质区，覆盖选择晶体管的第一绝缘夹层，与第一杂质区电连接的位线结构的选择晶体管，覆盖位线结构，通过第一和第二绝缘夹层形成的掺杂单晶硅插头，每个绝缘中间层接触第二杂质区并具有高于位线结构的高度，设置在插头上的有源图案和第二绝缘层夹层中的每个与插塞接触的铁电晶体管，以及设置在有源图案上的铁电晶体管，每个具有包括铁电层图案和导电图案的第二栅极结构，第三杂质区域和第四杂质区域。铁电存储器件执行随机存取操作并具有高集成度。

6. 发明授权

US07586774B2 Stacked ferroelectric memory devices, methods of manufacturing the same, ferroelectric memory circuits and methods of driving the same 失效
标题翻译：叠层铁电存储器件及其制造方法，铁电存储器电路及其驱动方法
公开(公告)号：US07586774B2
公开(公告)日：2009-09-08
申请号：US11675007
申请日：2007-02-14
申请人： Heung-Jin Joo , Byung-Gil Jeon , Byoung-Jae Bae , Ki-Nam Kim
发明人： Heung-Jin Joo , Byung-Gil Jeon , Byoung-Jae Bae , Ki-Nam Kim
IPC分类号： G11C11/22
CPC分类号： G11C11/22 , G11C11/221 , G11C11/223
摘要： A stacked ferroelectric memory device has selection transistors including a first gate structure, a first impurity region, a second impurity region, a first insulating interlayer covering the selection transistors, bit line structures electrically connected to the first impurity regions, a second insulating interlayer covering the bit line structures, doped single crystalline silicon plugs formed through the first and the second insulating interlayers, each of which contacts the second impurity region and has a height greater than that of the bit line structures, active patterns disposed on the plugs and the second insulating interlayer, each of which contacts the plugs, and ferroelectric transistors disposed on the active patterns, each of which has a second gate structure including a ferroelectric layer pattern and a conductive pattern, a third impurity region and a fourth impurity region. The ferroelectric memory device performs a random access operation and has a high degree of integration.
摘要翻译：堆叠的铁电存储器件具有包括第一栅极结构，第一杂质区，第二杂质区，覆盖选择晶体管的第一绝缘夹层，与第一杂质区电连接的位线结构的选择晶体管，覆盖位线结构，通过第一和第二绝缘夹层形成的掺杂单晶硅插头，每个绝缘中间层接触第二杂质区并具有高于位线结构的高度，设置在插头上的有源图案和第二绝缘层夹层中的每个与插塞接触的铁电晶体管，以及设置在有源图案上的铁电晶体管，每个具有包括铁电层图案和导电图案的第二栅极结构，第三杂质区域和第四杂质区域。铁电存储器件执行随机存取操作并具有高集成度。

7. 发明授权

US07052951B2 Ferroelectric memory devices with enhanced ferroelectric properties and methods for fabricating such memory devices 失效
标题翻译：具有增强的铁电性能的铁电存储器件和用于制造这种存储器件的方法
公开(公告)号：US07052951B2
公开(公告)日：2006-05-30
申请号：US10776394
申请日：2004-02-11
申请人： Heung-Jin Joo , Ki-Nam Kim
发明人： Heung-Jin Joo , Ki-Nam Kim
IPC分类号： H01L21/8242
CPC分类号： H01L27/11502 , H01L27/11507 , H01L28/55
摘要： Ferroelectric memory devices and methods for fabricating such devices are provided. The ferroelectric memory device may comprise one or more interlayer dielectric layers on a semiconductor substrate, an oxygen-diffusion barrier pattern on the interlayer dielectric layer(s), and an upper insulating layer that is on the interlayer dielectric layer(s) that at least partially surrounds the oxygen-diffusion barrier pattern. These devices further include a capacitor that has a bottom electrode that is on the oxygen-diffusion barrier layer and on at least a portion of the upper insulating layer, a ferroelectric layer that is on the bottom electrode, and a top electrode that is on the ferroelectric layer. In some embodiments of the present invention, the top surface of the upper insulating layer is higher than the top surface of the oxygen-diffusion barrier pattern.
摘要翻译：提供铁电存储器件及其制造方法。铁电存储器件可以包括在半导体衬底上的一个或多个层间电介质层，层间绝缘层上的氧扩散阻挡图案，以及至少在层间绝缘层上的上绝缘层部分地包围氧扩散阻挡图案。这些器件还包括具有位于氧扩散阻挡层上的底部电极和位于上部绝缘层的至少一部分上的电容器，位于底部电极上的铁电层，以及位于该底部电极上的顶部电极铁电层。在本发明的一些实施例中，上绝缘层的顶表面高于氧扩散阻挡图案的顶表面。

8. 发明授权

US07560760B2 Ferroelectric memory devices having expanded plate lines 失效
标题翻译：具有扩展板线的铁电存储器件
公开(公告)号：US07560760B2
公开(公告)日：2009-07-14
申请号：US11859958
申请日：2007-09-24
申请人： Hyun-Ho Kim , Dong-Jin Jung , Ki-Nam Kim , Sang-Don Nam , Kyu-Mann Lee
发明人： Hyun-Ho Kim , Dong-Jin Jung , Ki-Nam Kim , Sang-Don Nam , Kyu-Mann Lee
IPC分类号： H01L27/115
CPC分类号： H01L27/11502 , G11C11/22 , H01L27/11507
摘要： A ferroelectric memory device includes a microelectronic substrate and a plurality of ferroelectric capacitors on the substrate, arranged as a plurality of row and columns in respective row and column directions. A plurality of parallel plate lines overlie the ferroelectric capacitors and extend along the row direction, wherein a plate line contacts ferroelectric capacitors in at least two adjacent rows. The plurality of plate lines may include a plurality of local plate lines, and the ferroelectric memory device may further include an insulating layer disposed on the local plate lines and a plurality of main plate lines disposed on the insulating layer and contacting the local plate lines through openings in the insulating layer. In some embodiments, ferroelectric capacitors in adjacent rows share a common upper electrode, and respective ones of the local plate lines are disposed on respective ones of the common upper electrodes. Ferroelectric capacitors in adjacent rows may share a common ferroelectric dielectric region. Related fabrication methods are discussed.
摘要翻译：铁电存储器件包括微电子衬底和在衬底上的多个铁电电容器，被布置为在行和列方向上的多个行和列。多个平行板线覆盖在铁电电容器上并沿着行方向延伸，其中板线在至少两个相邻行中接触铁电电容器。多个板线可以包括多个局部板线，并且铁电存储器件还可以包括设置在局部板线上的绝缘层和设置在绝缘层上的多个主板线，并且使本地板线通过绝缘层中的开口。在一些实施例中，相邻行中的铁电电容器共享公共上电极，并且各自的局部板线设置在相应的公共上电极上。相邻行中的铁电电容器可以共享公共铁电电介质区域。讨论相关的制造方法。

9. 发明申请

US20080025065A1 FERROELECTRIC MEMORY DEVICES HAVING EXPANDED PLATE LINES 失效
标题翻译：具有扩展板线的电磁存储器件
公开(公告)号：US20080025065A1
公开(公告)日：2008-01-31
申请号：US11859958
申请日：2007-09-24
申请人： Hyun-Ho Kim , Dong-Jin Jung , Ki-Nam Kim , Sang-Don Nam , Kyu-Mann Lee
发明人： Hyun-Ho Kim , Dong-Jin Jung , Ki-Nam Kim , Sang-Don Nam , Kyu-Mann Lee
IPC分类号： G11C11/22
CPC分类号： H01L27/11502 , G11C11/22 , H01L27/11507
摘要： A ferroelectric memory device includes a microelectronic substrate and a plurality of ferroelectric capacitors on the substrate, arranged as a plurality of row and columns in respective row and column directions. A plurality of parallel plate lines overlie the ferroelectric capacitors and extend along the row direction, wherein a plate line contacts ferroelectric capacitors in at least two adjacent rows. The plurality of plate lines may include a plurality of local plate lines, and the ferroelectric memory device may further include an insulating layer disposed on the local plate lines and a plurality of main plate lines disposed on the insulating layer and contacting the local plate lines through openings in the insulating layer. In some embodiments, ferroelectric capacitors in adjacent rows share a common upper electrode, and respective ones of the local plate lines are disposed on respective ones of the common upper electrodes. Ferroelectric capacitors in adjacent rows may share a common ferroelectric dielectric region. Related fabrication methods are discussed.
摘要翻译：铁电存储器件包括微电子衬底和在衬底上的多个铁电电容器，被布置为在行和列方向上的多个行和列。多个平行板线覆盖在铁电电容器上并沿着行方向延伸，其中板线在至少两个相邻行中接触铁电电容器。多个板线可以包括多个局部板线，并且铁电存储器件还可以包括设置在局部板线上的绝缘层和设置在绝缘层上的多个主板线，并且使本地板线通过绝缘层中的开口。在一些实施例中，相邻行中的铁电电容器共享公共上电极，并且各自的局部板线设置在相应的公共上电极上。相邻行中的铁电电容器可以共享公共铁电电介质区域。讨论相关的制造方法。

10. 发明授权

US06420744B1 Ferroelectric capacitor and method for fabricating ferroelectric capacitor 失效
标题翻译：铁电电容器和制造铁电电容器的方法
公开(公告)号：US06420744B1
公开(公告)日：2002-07-16
申请号：US09712159
申请日：2000-11-15
申请人： Hyun-Ho Kim , Ki-Nam Kim
发明人： Hyun-Ho Kim , Ki-Nam Kim
IPC分类号： H01L2976
CPC分类号： H01L27/11502 , H01L27/11507 , H01L28/55 , Y10S257/906
摘要： A method of forming a semiconductor device wherein a dummy cell region is defined at a periphery of a cell array region that includes a ferroelectric capacitor. A dummy capacitor is formed simultaneously at the dummy cell region when a ferroelectric capacitor is formed at the cell array region. Accordingly, plasma etching damage and electrical charge generation are concentrated on the dummy capacitor, thereby reducing plasma etching damage and electrical charge generation at the ferroelectric capacitor of the cell array region.
摘要翻译：一种形成半导体器件的方法，其中在包括铁电电容器的单元阵列区域的外围限定虚拟单元区域。当在单元阵列区域形成铁电电容器时，在虚设单元区域同时形成虚拟电容器。因此，等离子体蚀刻损伤和电荷产生集中在虚拟电容器上，从而减少电池阵列区域的铁电电容器处的等离子体蚀刻损伤和电荷产生。

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