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1. 发明申请

US20080113515A1 Methods of Forming Semiconductor Devices 审中-公开
标题翻译：形成半导体器件的方法
公开(公告)号：US20080113515A1
公开(公告)日：2008-05-15
申请号：US11874267
申请日：2007-10-18
申请人： Hyun-Chul Kim , Sung-Il Cho , Eun-Young Kang , Yong-Hyun Kwon , Jae-Seung Hwang
发明人： Hyun-Chul Kim , Sung-Il Cho , Eun-Young Kang , Yong-Hyun Kwon , Jae-Seung Hwang
IPC分类号： H01L21/302
CPC分类号： H01L21/3086 , H01L21/3088 , H01L21/823437 , H01L27/105 , H01L29/66621
摘要： A method of forming a semiconductor device is provided. The method includes preparing a semiconductor substrate to include a cell region and a peripheral region and forming a first mask layer on the semiconductor substrate. First hard mask patterns that are configured to expose the first mask layer are formed on the first mask layer in the cell region. A second mask layer that is configured to conformably cover the first hard mask patterns is formed. A second hard mask pattern is formed between the first hard mask patterns, wherein the second hard mask pattern is configured to contact a lateral surface of the second mask layer. The second mask layer interposed between the first hard mask patterns and the second hard mask pattern is removed. A plurality of trenches are etched in the semiconductor substrate of the cell region using the first hard mask patterns and the second hard mask pattern as a mask.
摘要翻译：提供一种形成半导体器件的方法。该方法包括制备半导体衬底以包括单元区域和外围区域，并在半导体衬底上形成第一掩模层。配置为暴露第一掩模层的第一硬掩模图案形成在单元区域中的第一掩模层上。形成被构造为顺应地覆盖第一硬掩模图案的第二掩模层。在第一硬掩模图案之间形成第二硬掩模图案，其中第二硬掩模图案被配置为接触第二掩模层的侧表面。插入在第一硬掩模图案和第二硬掩模图案之间的第二掩模层被去除。使用第一硬掩模图案和第二硬掩模图案作为掩模，在单元区域的半导体衬底中蚀刻多个沟槽。

2. 发明授权

US08461687B2 Semiconductor devices including bit line contact plug and buried channel array transistor, and semiconductor modules, electronic circuit boards and electronic systems including the same 有权
标题翻译：包括位线接触插头和掩埋沟道阵列晶体管的半导体器件，以及包括其的电子电路板和电子系统的半导体模块
公开(公告)号：US08461687B2
公开(公告)日：2013-06-11
申请号：US13072907
申请日：2011-03-28
申请人： Sung-Il Cho , Nam-Gun Kim , Jin-Young Kim , Hyun-Chul Yoon , Bong-Soo Kim , Kwan-Sik Cho
发明人： Sung-Il Cho , Nam-Gun Kim , Jin-Young Kim , Hyun-Chul Yoon , Bong-Soo Kim , Kwan-Sik Cho
IPC分类号： H01L29/40 , H01L29/66
CPC分类号： H01L23/528 , H01L23/535 , H01L27/1052 , H01L27/10873 , H01L27/10876 , H01L27/10885 , H01L27/10888 , H01L27/10894 , H01L27/10897 , H01L29/0649 , H01L29/42324 , H01L29/45 , H01L29/78 , H01L29/7827 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having a cell area and a peripheral area includes a semiconductor substrate, a cell insulating isolation region delimiting a cell active region of the semiconductor substrate in the cell area, a word line disposed within the semiconductor substrate in the cell area, a bit line contact plug disposed on the cell active region, a bit line disposed on the bit line contact plug, a peripheral insulating isolation region delimiting a peripheral active region of the semiconductor substrate in the peripheral area, and a peripheral transistor including a peripheral transistor lower electrode and a peripheral transistor upper electrode. The bit line contact plug is formed at the same level in the semiconductor device as the peripheral transistor lower electrode, and the bit line electrode is formed at the same level in the semiconductor device as the peripheral transistor upper electrode.
摘要翻译：具有单元区域和周边区域的半导体器件包括半导体基板，限定单元区域中的半导体基板的单元有源区域的单元绝缘隔离区域，设置在单元区域中的半导体基板内的字线，位设置在单元有源区上的线接触插塞，位线接触插头上的位线，限定周边区域中的半导体衬底的周边有源区域的外围绝缘隔离区域以及包括周边晶体管下电极的外围晶体管和周边晶体管上电极。位线接触插塞形成在半导体器件中与外围晶体管下电极相同的电平上，并且位线电极在半导体器件中形成为与外围晶体管上电极相同的电平。

3. 发明申请

US20110241102A1 SEMICONDUCTOR DEVICES INCLUDING BIT LINE CONTACT PLUG AND BURIED CHANNEL ARRAY TRANSISTOR, METHODS OF FABRICATING THE SAME, AND SEMICONDUCTOR MODULES, ELECTRONIC CIRCUIT BOARDS AND ELECTRONIC SYSTEMS INCLUDING THE SAME 有权
标题翻译：包括位线接触插头和布线通道阵列晶体管，其制造方法和半导体模块，电子电路板和包括其的电子系统的半导体器件
公开(公告)号：US20110241102A1
公开(公告)日：2011-10-06
申请号：US13072907
申请日：2011-03-28
申请人： Sung-Il Cho , Nam-Gun Kim , Jin-Young Kim , Hyun-Chul Yoon , Bong-Soo Kim , Kwan-Sik Cho
发明人： Sung-Il Cho , Nam-Gun Kim , Jin-Young Kim , Hyun-Chul Yoon , Bong-Soo Kim , Kwan-Sik Cho
IPC分类号： H01L29/78
CPC分类号： H01L23/528 , H01L23/535 , H01L27/1052 , H01L27/10873 , H01L27/10876 , H01L27/10885 , H01L27/10888 , H01L27/10894 , H01L27/10897 , H01L29/0649 , H01L29/42324 , H01L29/45 , H01L29/78 , H01L29/7827 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device having a cell area and a peripheral area includes a semiconductor substrate, a cell insulating isolation region delimiting a cell active region of the semiconductor substrate in the cell area, a word line disposed within the semiconductor substrate in the cell area, a bit line contact plug disposed on the cell active region, a bit line disposed on the bit line contact plug, a peripheral insulating isolation region delimiting a peripheral active region of the semiconductor substrate in the peripheral area, and a peripheral transistor including a peripheral transistor lower electrode and a peripheral transistor upper electrode. The bit line contact plug is formed at the same level in the semiconductor device as the peripheral transistor lower electrode, and the bit line electrode is formed at the same level in the semiconductor device as the peripheral transistor upper electrode.
摘要翻译：具有单元区域和周边区域的半导体器件包括半导体基板，限定单元区域中的半导体基板的单元有源区域的单元绝缘隔离区域，设置在单元区域中的半导体基板内的字线，位设置在单元有源区上的线接触插塞，位线接触插头上的位线，限定周边区域中的半导体衬底的周边有源区域的外围绝缘隔离区域以及包括周边晶体管下电极的外围晶体管和周边晶体管上电极。位线接触插塞形成在半导体器件中与外围晶体管下电极相同的电平上，并且位线电极在半导体器件中形成为与外围晶体管上电极相同的电平。

4. 发明授权

US07704828B2 Method of fabricating a semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US07704828B2
公开(公告)日：2010-04-27
申请号：US11741639
申请日：2007-04-27
申请人： Jung-Min Oh , Jeong-Nam Han , Chang-Ki Hong , Kun-Tack Lee , Dae-Hyuk Kang , Sung-Il Cho
发明人： Jung-Min Oh , Jeong-Nam Han , Chang-Ki Hong , Kun-Tack Lee , Dae-Hyuk Kang , Sung-Il Cho
IPC分类号： H01L21/8242
CPC分类号： H01L28/91
摘要： A method of fabricating a semiconductor device is provided. The method includes forming a mold for forming a storage electrode, forming sacrificial spacers at side walls of openings in the mold, forming a conductive film for a storage electrode along the inside of the openings, removing the mold by a wet etching process, removing the sacrificial spacers by a dry etching process, and sequentially forming a dielectric film and an upper electrode on the storage electrode.
摘要翻译：提供一种制造半导体器件的方法。该方法包括形成用于形成存储电极的模具，在模具的开口的侧壁处形成牺牲隔离物，沿着开口的内部形成用于存储电极的导电膜，通过湿法蚀刻工艺移除模具，牺牲隔离物，并且在存储电极上依次形成电介质膜和上电极。

5. 发明授权

US07439566B2 Semiconductor memory device having metal-insulator transition film resistor 有权
标题翻译：具有金属 - 绝缘体转移膜电阻器的半导体存储器件
公开(公告)号：US07439566B2
公开(公告)日：2008-10-21
申请号：US11485340
申请日：2006-07-13
申请人： Jae-Woong Hyun , In-Kyeong Yoo , Yoon-Dong Park , Choong-Rae Cho , Sung-Il Cho
发明人： Jae-Woong Hyun , In-Kyeong Yoo , Yoon-Dong Park , Choong-Rae Cho , Sung-Il Cho
IPC分类号： H01L29/06
CPC分类号： H01L27/108 , H01L27/101 , H01L27/2436 , H01L45/146
摘要： A semiconductor memory device may have a lower leakage current and/or higher reliability, e.g., a longer retention time and/or a shorter refresh time. The device may include a switching device and a capacitor. A source of the switching device may be connected to a first end of a metal-insulator transition film resistor, and at least one electrode of the capacitor may be connected to a second end of the metal-insulator transition film resistor. The metal-insulator transition film resistor may transition between an insulator and a conductor according to a voltage supplied to the first and second ends thereof.
摘要翻译：半导体存储器件可以具有较低的漏电流和/或更高的可靠性，例如较长的保留时间和/或更短的刷新时间。该装置可以包括开关装置和电容器。开关器件的源极可以连接到金属 - 绝缘体转变膜电阻器的第一端，并且电容器的至少一个电极可以连接到金属 - 绝缘体转变膜电阻器的第二端。金属 - 绝缘体转变膜电阻器可以根据提供给其第一和第二端的电压在绝缘体和导体之间转变。

6. 发明授权

US07291531B2 Method of fabricating semiconductor device having capacitor 有权
标题翻译：制造具有电容器的半导体器件的方法
公开(公告)号：US07291531B2
公开(公告)日：2007-11-06
申请号：US11048995
申请日：2005-02-02
申请人： Sung-Il Cho , Seung-Young Son , Chang-Jin Kang , Kyeong-Koo Chi , Ji-Chul Shin
发明人： Sung-Il Cho , Seung-Young Son , Chang-Jin Kang , Kyeong-Koo Chi , Ji-Chul Shin
IPC分类号： H01L21/8242
CPC分类号： H01L28/91 , H01L21/3142 , H01L21/31616 , H01L21/31645 , H01L21/32136 , H01L27/10855
摘要： Methods are provided for fabricating semiconductor devices having capacitors, which prevent lower electrodes of the capacitors from breaking or collapsing and which provide increased capacitance of the capacitors. For instance, a method includes forming a first insulating layer on a semiconductor substrate, forming a first hole in the first insulating layer, forming a contact plug in the first hole, forming a second insulating layer having a landing pad, wherein the landing pad contacts an upper surface of the contact plug, forming an etch stop layer on the landing pad and the second insulating layer, forming a third insulating layer on the etch stop layer; forming a third hole through the third insulating layer and etch stop layer to expose the landing pad, selectively etching the exposed landing pad, forming a lower electrode on the selectively etched landing pad, and then forming a capacitor by forming a dielectric layer and an upper electrode on the lower electrode.
摘要翻译：提供了用于制造具有电容器的半导体器件的方法，其阻止电容器的下部电极断开或塌缩并且提供电容器的增加的电容。例如，一种方法包括在半导体衬底上形成第一绝缘层，在第一绝缘层中形成第一孔，在第一孔中形成接触塞，形成具有着陆垫的第二绝缘层，其中，接触插塞的上表面，在着陆焊盘和第二绝缘层上形成蚀刻停止层，在蚀刻停止层上形成第三绝缘层; 通过第三绝缘层和蚀刻停止层形成第三孔以暴露着陆焊盘，选择性地蚀刻暴露的着陆焊盘，在选择性蚀刻的焊盘上形成下电极，然后通过形成电介质层和上层电极在下电极上。

7. 发明授权

US08043926B2 Nonvolatile memory devices including oxygen-deficient metal oxide layers and methods of manufacturing the same 有权
公开(公告)号：US08043926B2
公开(公告)日：2011-10-25
申请号：US12926042
申请日：2010-10-22
申请人： Sung-Il Cho , Choong-rae Cho , Eun-hong Lee , In-kyeong Yoo
发明人： Sung-Il Cho , Choong-rae Cho , Eun-hong Lee , In-kyeong Yoo
IPC分类号： H01L21/02
CPC分类号： H01L27/115 , G11C13/0007 , G11C2213/32 , G11C2213/51 , H01L27/112 , H01L27/2436 , H01L45/04 , H01L45/1233 , H01L45/146
摘要： A nonvolatile memory device includes at least one switching device and at least one storage node electrically connected to the at least one switching device. The at least one storage node includes a lower electrode, one or more oxygen-deficient metal oxide layers, one or more data storage layers, and an upper electrode. At least one of the one or more metal oxide layers is electrically connected to the lower electrode. At least one of the one or more data storage layers is electrically connected to at least one of the one or more metal oxide layers. The upper electrode is electrically connected to at least one of the one or more data storage layers. A method of manufacturing the nonvolatile memory device includes preparing the at least one switching device and forming the lower electrode, one or more metal oxide layers, one or more data storage layers, and upper electrode.

8. 发明申请

US20080087931A1 METHOD OF FABRICATING SEMICONDUCTOR DEVICE HAVING CAPACITOR 有权
标题翻译：制造具有电容器的半导体器件的方法
公开(公告)号：US20080087931A1
公开(公告)日：2008-04-17
申请号：US11869400
申请日：2007-10-09
申请人： Sung-Il Cho , Seung-Young Son , Chang-Jin Kang , Kyeong-Koo Chi , Ji-Chul Shin
发明人： Sung-Il Cho , Seung-Young Son , Chang-Jin Kang , Kyeong-Koo Chi , Ji-Chul Shin
IPC分类号： H01L27/108 , H01L21/3205 , H01L21/8242
CPC分类号： H01L28/91 , H01L21/3142 , H01L21/31616 , H01L21/31645 , H01L21/32136 , H01L27/10855
摘要： Methods are provided for fabricating semiconductor devices having capacitors, which prevent lower electrodes of the capacitors from breaking or collapsing and which provide increased capacitance of the capacitors. For instance, a method includes forming a first insulating layer on a semiconductor substrate, forming a first hole in the first insulating layer, forming a contact plug in the first hole, forming a second insulating layer having a landing pad, wherein the landing pad contacts an upper surface of the contact plug, forming an etch stop layer on the landing pad and the second insulating layer, forming a third insulating layer on the etch stop layer, forming a third hole through the third insulating layer and etch stop layer to expose the landing pad, selectively etching the exposed landing pad, forming a lower electrode on the selectively etched landing pad, and then forming a capacitor by forming a dielectric layer and an upper electrode on the lower electrode.
摘要翻译：提供了用于制造具有电容器的半导体器件的方法，其阻止电容器的下部电极断开或塌缩并且提供电容器的增加的电容。例如，一种方法包括在半导体衬底上形成第一绝缘层，在第一绝缘层中形成第一孔，在第一孔中形成接触塞，形成具有着陆垫的第二绝缘层，其中，所述接触插塞的上表面在所述着陆焊盘和所述第二绝缘层上形成蚀刻停止层，在所述蚀刻停止层上形成第三绝缘层，形成通过所述第三绝缘层的第三孔和蚀刻停止层，选择性地蚀刻暴露的着陆焊盘，在选择性蚀刻的着陆焊盘上形成下电极，然后通过在下电极上形成电介质层和上电极来形成电容器。

9. 发明申请

US20070257257A1 Nonvolatile memory device including amorphous alloy metal oxide layer and method of manufacturing the same 有权
标题翻译：包括非晶合金金属氧化物层的非易失性存储器件及其制造方法
公开(公告)号：US20070257257A1
公开(公告)日：2007-11-08
申请号：US11704365
申请日：2007-02-09
申请人： Choong-Rae Cho , Sung-Il Cho , In-Kyeong Yoo , Eun-Hong Lee , Chang-Wook Moon
发明人： Choong-Rae Cho , Sung-Il Cho , In-Kyeong Yoo , Eun-Hong Lee , Chang-Wook Moon
IPC分类号： H01L29/86 , H01L21/34 , H01L29/24
CPC分类号： H01L27/2409 , H01L21/31691 , H01L29/47 , H01L45/04 , H01L45/1233 , H01L45/146
摘要： A nonvolatile memory device may include a lower electrode, an oxide layer including an amorphous alloy metal oxide disposed on the lower electrode, and a diode structure disposed on the oxide layer.
摘要翻译：非易失性存储器件可以包括下电极，包括设置在下电极上的非晶合金金属氧化物的氧化物层和设置在氧化物层上的二极管结构。

10. 发明申请

US20060255392A1 Transistor including metal-insulator transition material and method of manufacturing the same 审中-公开
标题翻译：包括金属 - 绝缘体过渡材料的晶体管及其制造方法
公开(公告)号：US20060255392A1
公开(公告)日：2006-11-16
申请号：US11432620
申请日：2006-05-12
申请人： Choong-Rae Cho , In-Kyeong Yoo , Yang-Kyu Choi , Sung-Il Cho
发明人： Choong-Rae Cho , In-Kyeong Yoo , Yang-Kyu Choi , Sung-Il Cho
IPC分类号： H01L29/94
CPC分类号： H01L49/003
摘要： A transistor including a metal-insulation transition material and a method of manufacturing the same. The transistor including a metal-insulator transition material may include a substrate, a insulation layer formed on the substrate, a source region and a drain region separately formed from each other on the insulation layer, a tunneling barrier layer formed on at least one surface of the source region and the drain region, a metal-insulator transition material layer formed on the tunneling barrier layer and the insulation layer, a dielectric layer stacked on the metal-insulator transition material layer, and a gate electrode layer formed on the dielectric layer.
摘要翻译：一种包括金属绝缘过渡材料的晶体管及其制造方法。包括金属 - 绝缘体转移材料的晶体管可以包括基板，形成在基板上的绝缘层，在绝缘层上彼此分开形成的源极区域和漏极区域，形成在绝缘层的至少一个表面上的隧道势垒层源极区域和漏极区域，形成在隧道势垒层和绝缘层上的金属 - 绝缘体转移材料层，堆叠在金属 - 绝缘体转移材料层上的电介质层和形成在电介质层上的栅极电极层。

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