专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07002872B2 Semiconductor memory device with a decoupling capacitor 失效
标题翻译：具有去耦电容器的半导体存储器件
公开(公告)号：US07002872B2
公开(公告)日：2006-02-21
申请号：US10676996
申请日：2003-09-30
申请人： Hyong-ryol Hwang , Young-hun Seo , Jae-yoon Sim
发明人： Hyong-ryol Hwang , Young-hun Seo , Jae-yoon Sim
IPC分类号： G11C8/00
CPC分类号： G11C5/063
摘要： A semiconductor memory device includes a core block having sub-arrays and sense amplifier regions. First and second charge storing regions are disposed at sides of the core block. First and second decoupling capacitors are formed at the first and second charge storing regions, respectively. A plurality of first voltage supply lines are disposed to supply a power supply voltage to the sense amplifier regions and are connected to one electrode of each of the first and second decoupling capacitors. A plurality of second voltage supply lines are disposed to supply a ground voltage to the sense amplifier regions and are connected to the other electrode of each of the first and second decoupling capacitors.
摘要翻译：半导体存储器件包括具有子阵列和读出放大器区域的核心块。第一和第二电荷存储区域设置在芯块的侧面。分别在第一和第二电荷存储区域形成第一和第二去耦电容器。设置多个第一电压供应线，以将电源电压提供给感测放大器区域，并且连接到第一和第二去耦电容器中的每一个的一个电极。设置多个第二电压供给线，以将接地电压提供给读出放大器区域，并连接到第一和第二去耦电容器中的每一个的另一个电极。

2. 发明授权

US06275066B1 Current-mode bidirectional input/output buffer for impedance matching 失效
标题翻译：用于阻抗匹配的电流模式双向输入/输出缓冲器
公开(公告)号：US06275066B1
公开(公告)日：2001-08-14
申请号：US09545461
申请日：2000-04-07
申请人： Hong-june Park , Jae-yoon Sim
发明人： Hong-june Park , Jae-yoon Sim
IPC分类号： H03K190175
CPC分类号： H03K19/018578 , H03K19/018592
摘要： A current-mode bidirectional input/output buffer circuit for impedance matching and operation at a high speed. The current-mode bidirectional input/output buffer circuit communicates with an external chip having the same current-mode bidirectional input/output buffer. In the buffer, a transmitting-receiving average voltage output unit converts an average current value between a transmission signal to be transmitted to the external chip and a receiving signal transmitted from the external chip, into an average voltage. A reference voltage output unit converts a reference current value selectively generated according to a voltage level of the transmission signal, into a reference voltage. A comparator compares the voltage from the transmitting-receiving average voltage output unit to the voltage from the reference voltage output unit to provide a logic signal corresponding to the received signal transmitted from the external chip. A bias voltage generator generates a bias voltage such that the impedance of each output unit is matched with a characteristic impedance of a transmission line coupled to the external chip, and provides the bias voltage to the transmitting-receiving average voltage output unit and the reference voltage output unit. Accordingly, the current-mode bidirectional input/output buffer transmits data between chips at a high rate using a single transmission line and is stable in spite of variations in processes for fabricating chips.
摘要翻译：一种用于阻抗匹配和高速运行的电流模式双向输入/输出缓冲电路。电流模式双向输入/输出缓冲电路与具有相同电流模式双向输入/输出缓冲器的外部芯片通信。在缓冲器中，发送接收平均电压输出单元将要发送的发送信号与外部芯片的发送信号与从外部芯片发送的接收信号之间的平均电流值转换为平均电压。参考电压输出单元将根据发送信号的电压电平有选择地生成的参考电流值转换为参考电压。比较器将来自发送接收平均电压输出单元的电压与来自参考电压输出单元的电压进行比较，以提供与从外部芯片发送的接收信号相对应的逻辑信号。偏置电压发生器产生偏置电压，使得每个输出单元的阻抗与耦合到外部芯片的传输线的特性阻抗匹配，并将偏置电压提供给发射接收平均电压输出单元和参考电压输出单元。因此，电流模式双向输入/输出缓冲器使用单个传输线以高速率在芯片之间传输数据，并且尽管制造芯片的工艺的变化是稳定的。

3. 发明授权

US06983010B1 High frequency equalizer using a demultiplexing technique and related semiconductor device 有权
标题翻译：使用解复用技术的高频均衡器和相关的半导体器件
公开(公告)号：US06983010B1
公开(公告)日：2006-01-03
申请号：US09542042
申请日：2000-03-31
申请人： Jae-yoon Sim , Hong-joon Park , Soo-in Cho , Jung-bae Lee
发明人： Jae-yoon Sim , Hong-joon Park , Soo-in Cho , Jung-bae Lee
IPC分类号： H03H7/30
CPC分类号： G11C7/1057 , G11C7/1012 , G11C7/1051 , G11C7/22 , G11C7/222 , H01L27/088 , H04L27/01
摘要： A high frequency equalizer using a demultiplexing technique and a semiconductor device using the same are provided. The high frequency equalizer demultiplexes input data input through an input and output terminal into a plurality of input data items, each having a time difference that is the same as the period of the input data. The equalizer restores the lost high frequency data components of the plurality of demultiplexed input data items, multiplexes the restored plurality of data items, and sequentially outputs the restored data items one by one. Therefore, using this high frequency equalizer, it is possible to allow enough time to restore the lost high frequency component even though the period of the input data is reduced by an increase of the data transmission speed. Using this high frequency equalizer, it is possible to correctly restore the lost high frequency component even at a high data transmission speed. Therefore, according to the semiconductor device including the high frequency equalizer, the lost high frequency component of data can be restored even at a high data transmission speed.
摘要翻译：提供了使用解复用技术的高频均衡器和使用其的半导体器件。高频均衡器将通过输入和输出端输入的输入数据解复用为多个输入数据项，每个具有与输入数据周期相同的时间差。均衡器恢复多路复用输入数据项的丢失的高频数据分量，复用恢复的多个数据项，并逐个依次输出恢复的数据项。因此，即使通过数据传输速度的增加来减少输入数据的周期，也可以使用这种高频均衡器来允许足够的时间来恢复丢失的高频分量。使用该高频均衡器，即使在高数据传输速度下也可以正确地恢复丢失的高频分量。因此，根据包括高频均衡器的半导体器件，即使在高数据传输速度下也可以恢复数据的丢失高频分量。

4. 发明授权

US07705644B2 Broadband multi-phase output delay locked loop circuit utilizing a delay matrix 有权
标题翻译：使用延迟矩阵的宽带多相输出延迟锁定环路电路
公开(公告)号：US07705644B2
公开(公告)日：2010-04-27
申请号：US12028936
申请日：2008-02-11
申请人： Ho-young Kim , Dong-bee Jang , Jae-yoon Sim , Young-sang Kim
发明人： Ho-young Kim , Dong-bee Jang , Jae-yoon Sim , Young-sang Kim
IPC分类号： H03L7/06
CPC分类号： H03L7/0812 , H03L7/10
摘要： A broadband multi-phase output delay locked loop (DLL) circuit can be operated in a wide range of frequencies and generate various phases. Unlike conventional voltage control delay lines in which delay cells are connected in series, the DLL circuit utilizes a delay matrix in which a resistant network is used so that the number of delay cells connected in series is reduced, various phases can be outputted, and a delay interval error (phase error) due to the resistant network is minimized. The current of the delay cells is controlled so that the delay cells in the delay matrix can operate in a wide range of frequencies, and load capacitance values of capacitors connected in parallel in the delay cells can be controlled.
摘要翻译：宽带多相输出延迟锁定环（DLL）电路可以在宽频率范围内工作，并产生各种相位。与其中延迟单元串联连接的常规电压控制延迟线不同，DLL电路利用其中使用电阻网络的延迟矩阵，使得串联连接的延迟单元的数量减少，可以输出各种相位，并且由于抵抗网络导致的延迟间隔误差（相位误差）被最小化。控制延迟单元的电流，使得延迟矩阵中的延迟单元可以在宽的频率范围内工作，并且可以控制在延迟单元中并联连接的电容器的负载电容值。

5. 发明授权

US07113436B2 Sense amplifying circuit for a semiconductor memory with improved data read ability at a low supply voltage 失效
标题翻译：用于半导体存储器的感测放大电路，其在低电源电压下具有改善的数据读取能力
公开(公告)号：US07113436B2
公开(公告)日：2006-09-26
申请号：US10731841
申请日：2003-12-09
申请人： Seung-hoon Lee , Jae-yoon Sim
发明人： Seung-hoon Lee , Jae-yoon Sim
IPC分类号： G11C7/02
CPC分类号： G11C7/062
摘要： Provided is a circuit for use in a semiconductor memory optimized to improve data read ability at low supply voltages. Circuit includes a direct sense AMP circuit, an input/output gate circuit, and an operation control unit. The direct sense AMP circuit transmits read data loaded in a bit line pair including first and second bit lines to a data input/output pair including first and second data input/output lines in response to a read command signal. The input/output gate circuit which, in response to a read/write signal, also passes the read data loaded in the bit line pair directly to the data input/output line pair, and passes write data loaded in the data input/output line pair directly to the bit line pair. The operation control unit which, in response to a column address signal and a write command, generates the read command signal and the read/write signal to turn ON both the direct sense AMP circuit and the input/output gate circuit in a data read operation, or to turn ON the input/output gate circuit and turn OFF the direct sense AMP circuit in a data write operation.
摘要翻译：提供了一种用于半导体存储器中的电路，其被优化以在低电源电压下提高数据读取能力。电路包括直接感测AMP电路，输入/输出门电路和操作控制单元。直接感测放大器电路响应于读取命令信号，将包括第一和第二位线的位线对中的读取数据传输到包括第一和第二数据输入/输出线的数据输入/输出对。输入/输出门电路响应于读/写信号也将加载在位线对中的读数据直接传送到数据输入/输出线对，并将加载在数据输入/输出线直接对位线对。操作控制单元，响应于列地址信号和写命令，产生读指令信号和读/写信号，以在数据读操作中接通直接检测AMP电路和输入/输出门电路或者在数据写入操作中打开输入/输出门电路并关闭直接感测AMP电路。

6. 发明授权

US06476646B2 Sense amplifier of semiconductor integrated circuit 失效
标题翻译：半导体集成电路的感应放大器
公开(公告)号：US06476646B2
公开(公告)日：2002-11-05
申请号：US09956577
申请日：2001-09-18
申请人： Jae-yoon Sim , Hyun-soon Jang , Woo-seop Jeong , Kyung-ho Kim
发明人： Jae-yoon Sim , Hyun-soon Jang , Woo-seop Jeong , Kyung-ho Kim
IPC分类号： G01R1900
CPC分类号： H03F3/347 , G11C7/062 , G11C7/065 , H03F3/45183 , H03F3/4565 , H03F3/72 , H03F2203/45418 , H03F2203/45562 , H03F2203/45571 , H03F2203/45574 , H03F2203/45644 , H03F2203/45652 , H03F2203/45674 , H03K5/2481
摘要： A semiconductor integrated circuit includes a sense amplifier for amplifying an input signal and a complement of the input signal. The sense amplifier includes cross-coupled transistors. Each unique cross-coupled transistor is coupled to a corresponding unique transistor formed as a diode. A resistor is coupled in series between one cross-coupled resistor and an input port receiving the input signal, and another resistor is coupled in series between the other cross-coupled transistor and another input port receiving the complement of the input signal. Resistances associated with the sources of each cross-coupled transistor provide the resistance of the resistors.
摘要翻译：半导体集成电路包括用于放大输入信号的读出放大器和输入信号的补码。读出放大器包括交叉耦合晶体管。每个独特的交叉耦合晶体管耦合到形成为二极管的对应的唯一晶体管。电阻器串联耦合在一个交叉耦合电阻器和接收输入信号的输入端口之间，另一个电阻器串联耦合在另一个交叉耦合晶体管和另一个输入端口，该输入端口接收输入信号的补码。与每个交叉耦合晶体管的源极相关的电阻提供了电阻器的电阻。

7. 发明授权

US06326815B1 Sense amplifier of semiconductor integrated circuit 失效
标题翻译：半导体集成电路的感应放大器
公开(公告)号：US06326815B1
公开(公告)日：2001-12-04
申请号：US09547987
申请日：2000-04-12
申请人： Jae-yoon Sim , Hyun-soon Jang , Woo-seop Jeong , Kyung-ho Kim
发明人： Jae-yoon Sim , Hyun-soon Jang , Woo-seop Jeong , Kyung-ho Kim
IPC分类号： G01R1900
CPC分类号： H03F3/347 , G11C7/062 , G11C7/065 , H03F3/45183 , H03F3/4565 , H03F3/72 , H03F2203/45418 , H03F2203/45562 , H03F2203/45571 , H03F2203/45574 , H03F2203/45644 , H03F2203/45652 , H03F2203/45674 , H03K5/2481
摘要： A semiconductor integrated circuit includes a sense amplifier for amplifying an input signal and an complementary input signal, a full differential amplifier for amplifying the output of the sense amplifier, and a latch for latching the output of the full differential amplifier and outputting the latched output. The full differential amplifier includes a first differential amplifying unit for increasing the voltage of an output port when the level of an input signal input through an input port is larger than the level of an complementary input signal input through an complementary input port and reducing the voltage of the output port when the level of the input signal is lower than the level of the complementary input signal, a second differential amplifying unit for reducing the voltage of an complementary output port when the level of the input signal is larger than the level of the complementary input signal and increasing the voltage of the complementary output port when the level of the input signal is lower than the level of the complementary input signal, and an output voltage level control circuit connected between the output port and the complementary output port. The output voltage level control circuit controls the voltage levels of the output signals output from the output port and the complementary output port. The sense amplifier can stabilize the operation of the latch by reducing the mean voltage level of the output signal even when the supply A voltage increases, can easily control the voltage gain of the full differential amplifier by controlling the resistance, and stably operates at high speed. The current sense amplifier can include resistors associated with PMOS transistors to avoid unstable operation caused by increased transconductance arising from higher operating voltage.
摘要翻译：半导体集成电路包括用于放大输入信号和互补输入信号的读出放大器，用于放大读出放大器的输出的全差分放大器和用于锁存全差分放大器的输出并输出锁存输出的锁存器。全差分放大器包括第一差分放大单元，用于当通过输入端口输入的输入信号的电平大于通过互补输入端口输入的互补输入信号的电平时，增加输出端口的电压，并降低电压当所述输入信号的电平低于所述互补输入信号的电平时，所述第二差分放大单元用于当所述输入信号的电平大于所述输入信号的电平时降低互补输出端口的电压; 互补输入信号，并且当输入信号的电平低于互补输入信号的电平时增加互补输出端口的电压，以及连接在输出端口和互补输出端口之间的输出电压电平控制电路。输出电压电平控制电路控制从输出端口和互补输出端口输出的输出信号的电压电平。读出放大器可以通过降低输出信号的平均电压电平来稳定锁存器的操作，即使电源A电压增加，也可以通过控制电阻容易地控制全差分放大器的电压增益，并可以高速稳定运行。电流检测放大器可以包括与PMOS晶体管相关联的电阻器，以避免由于较高工作电压引起的跨导增加引起的不稳定操作。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式