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1. 发明申请

US20050218434A1 Transistor having asymmetric channel region, semiconductor device including the same, and method of fabricating semiconductor device including the same 有权
标题翻译：具有不对称沟道区的晶体管，包括该晶体管的半导体器件及其制造方法
公开(公告)号：US20050218434A1
公开(公告)日：2005-10-06
申请号：US11100685
申请日：2005-04-06
申请人： Hyeoung-Won Seo , Du-Heon Song , Sun-Joon Kim , Jin-Woo Lee
发明人： Hyeoung-Won Seo , Du-Heon Song , Sun-Joon Kim , Jin-Woo Lee
IPC分类号： H01L21/336 , H01L21/8242 , H01L27/108 , H01L29/78
CPC分类号： H01L27/10873 , H01L27/10876 , H01L29/66621 , H01L29/66659 , H01L29/7834
摘要： According to embodiments of the invention, a transistor includes a semiconductor substrate having an active region. A channel trench is disposed to cross the active region. A gate insulating layer covers an inner wall of the channel trench. A gate pattern is disposed to fill the channel trench and to extend over a main surface of the semiconductor substrate. Source/drain regions having a first conductivity are disposed in the active region at both sides of the channel trench. A channel impurity region having a second conductivity is disposed beneath one of the source/drain regions to be in contact with at least a sidewall of the channel trench.
摘要翻译：根据本发明的实施例，晶体管包括具有有源区的半导体衬底。通道槽被设置成穿过有源区域。栅极绝缘层覆盖沟道沟槽的内壁。设置栅极图案以填充沟道沟槽并在半导体衬底的主表面上延伸。具有第一导电性的源极/漏极区域设置在沟道沟槽的两侧的有源区域中。在源极/漏极区之一下方设置具有第二导电性的沟道杂质区，以与沟道沟槽的至少一个侧壁接触。

2. 发明授权

US07354827B2 Transistor having asymmetric channel region, semiconductor device including the same, and method of fabricating semiconductor device including the same 有权
标题翻译：具有不对称沟道区的晶体管，包括该晶体管的半导体器件及其制造方法
公开(公告)号：US07354827B2
公开(公告)日：2008-04-08
申请号：US11100685
申请日：2005-04-06
申请人： Hyeoung-Won Seo , Du-Heon Song , Sun-Joon Kim , Jin-Woo Lee
发明人： Hyeoung-Won Seo , Du-Heon Song , Sun-Joon Kim , Jin-Woo Lee
IPC分类号： H01L21/336
CPC分类号： H01L27/10873 , H01L27/10876 , H01L29/66621 , H01L29/66659 , H01L29/7834
摘要： According to embodiments of the invention, a transistor includes a semiconductor substrate having an active region. A channel trench is disposed to cross the active region. A gate insulating layer covers an inner wall of the channel trench. A gate pattern is disposed to fill the channel trench and to extend over a main surface of the semiconductor substrate. Source/drain regions having a first conductivity are disposed in the active region at both sides of the channel trench. A channel impurity region having a second conductivity is disposed beneath one of the source/drain regions to be in contact with at least a sidewall of the channel trench.
摘要翻译：根据本发明的实施例，晶体管包括具有有源区的半导体衬底。通道槽被设置成穿过有源区域。栅极绝缘层覆盖沟道沟槽的内壁。设置栅极图案以填充沟道沟槽并在半导体衬底的主表面上延伸。具有第一导电性的源极/漏极区域设置在沟道沟槽的两侧的有源区域中。在源极/漏极区之一下方设置具有第二导电性的沟道杂质区，以与沟道沟槽的至少一个侧壁接触。

3. 发明授权

US07247541B2 Method of manufacturing a semiconductor memory device including a transistor 失效
标题翻译：制造包括晶体管的半导体存储器件的方法
公开(公告)号：US07247541B2
公开(公告)日：2007-07-24
申请号：US11171710
申请日：2005-06-30
申请人： Jin-Woo Lee , Cheol-Ju Yun , Hyeoung-Won Seo
发明人： Jin-Woo Lee , Cheol-Ju Yun , Hyeoung-Won Seo
IPC分类号： H01L21/336
CPC分类号： H01L27/10814 , H01L27/10823 , H01L27/10852 , H01L27/10873 , H01L27/10876 , H01L27/10885 , H01L27/10888 , H01L28/91 , H01L29/6659
摘要： A semiconductor device comprises a plurality of gate structures formed on a substrate, a gate spacer formed on a sidewall of the gate structures, a semiconductor pattern formed on the substrate between the gate structures, a first impurity region and a second impurity region formed in the semiconductor pattern and at surface portions of the substrate, respectively, wherein the first and second impurity regions include a first conductive type impurity, and a channel doping region surrounding the first impurity region, wherein the channel doping region includes a second conductive type impurity.
摘要翻译：半导体器件包括形成在衬底上的多个栅极结构，形成在栅极结构的侧壁上的栅极间隔物，形成在栅极结构之间的衬底上的半导体图案，形成在栅极结构中的第一杂质区域和第二杂质区域半导体图案和衬底的表面部分，其中第一和第二杂质区域包括第一导电类型杂质和围绕第一杂质区的沟道掺杂区域，其中沟道掺杂区域包括第二导电类型杂质。

4. 发明授权

US07557410B2 Dynamic random access memory device 有权
标题翻译：动态随机存取存储器
公开(公告)号：US07557410B2
公开(公告)日：2009-07-07
申请号：US11769260
申请日：2007-06-27
申请人： Jin-Woo Lee , Cheol-Ju Yun , Hyeoung-Won Seo
发明人： Jin-Woo Lee , Cheol-Ju Yun , Hyeoung-Won Seo
IPC分类号： H01L29/76 , H01L29/94 , H01L31/00
CPC分类号： H01L27/10814 , H01L27/10823 , H01L27/10852 , H01L27/10873 , H01L27/10876 , H01L27/10885 , H01L27/10888 , H01L28/91 , H01L29/6659
摘要： A semiconductor device comprises a plurality of gate structures formed on a substrate, a gate spacer formed on a sidewall of the gate structures, a semiconductor pattern formed on the substrate between the gate structures, a first impurity region and a second impurity region formed in the semiconductor pattern and at surface portions of the substrate, respectively, wherein the first and second impurity regions include a first conductive type impurity, and a channel doping region surrounding the first impurity region, wherein the channel doping region includes a second conductive type impurity.
摘要翻译：半导体器件包括形成在衬底上的多个栅极结构，形成在栅极结构的侧壁上的栅极间隔物，形成在栅极结构之间的衬底上的半导体图案，形成在栅极结构中的第一杂质区域和第二杂质区域半导体图案和衬底的表面部分，其中第一和第二杂质区域包括第一导电类型杂质和围绕第一杂质区的沟道掺杂区域，其中沟道掺杂区域包括第二导电类型杂质。

5. 发明授权

US07482222B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07482222B2
公开(公告)日：2009-01-27
申请号：US11769276
申请日：2007-06-27
申请人： Jin-Woo Lee , Cheol-Ju Yun , Hyeoung-Won Seo
发明人： Jin-Woo Lee , Cheol-Ju Yun , Hyeoung-Won Seo
IPC分类号： H01L21/8242
CPC分类号： H01L27/10814 , H01L27/10823 , H01L27/10852 , H01L27/10873 , H01L27/10876 , H01L27/10885 , H01L27/10888 , H01L28/91 , H01L29/6659
摘要： A semiconductor device comprises a plurality of gate structures formed on a substrate, a gate spacer formed on a sidewall of the gate structures, a semiconductor pattern formed on the substrate between the gate structures, a first impurity region and a second impurity region formed in the semiconductor pattern and at surface portions of the substrate, respectively, wherein the first and second impurity regions include a first conductive type impurity, and a channel doping region surrounding the first impurity region, wherein the channel doping region includes a second conductive type impurity.
摘要翻译：半导体器件包括形成在衬底上的多个栅极结构，形成在栅极结构的侧壁上的栅极间隔物，形成在栅极结构之间的衬底上的半导体图案，形成在栅极结构中的第一杂质区域和第二杂质区域半导体图案和衬底的表面部分，其中第一和第二杂质区域包括第一导电类型杂质和围绕第一杂质区的沟道掺杂区域，其中沟道掺杂区域包括第二导电类型杂质。

6. 发明申请

US20080014695A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080014695A1
公开(公告)日：2008-01-17
申请号：US11769276
申请日：2007-06-27
申请人： Jin-Woo Lee , Cheol-Ju Yun , Hyeoung-Won Seo
发明人： Jin-Woo Lee , Cheol-Ju Yun , Hyeoung-Won Seo
IPC分类号： H01L21/8242 , H01L21/336
CPC分类号： H01L27/10814 , H01L27/10823 , H01L27/10852 , H01L27/10873 , H01L27/10876 , H01L27/10885 , H01L27/10888 , H01L28/91 , H01L29/6659
摘要： A semiconductor device comprises a plurality of gate structures formed on a substrate, a gate spacer formed on a sidewall of the gate structures, a semiconductor pattern formed on the substrate between the gate structures, a first impurity region and a second impurity region formed in the semiconductor pattern and at surface portions of the substrate, respectively, wherein the first and second impurity regions include a first conductive type impurity, and a channel doping region surrounding the first impurity region, wherein the channel doping region includes a second conductive type impurity.
摘要翻译：半导体器件包括形成在衬底上的多个栅极结构，形成在栅极结构的侧壁上的栅极间隔物，形成在栅极结构之间的衬底上的半导体图案，形成在栅极结构中的第一杂质区域和第二杂质区域半导体图案和衬底的表面部分，其中第一和第二杂质区域包括第一导电类型杂质和围绕第一杂质区的沟道掺杂区域，其中沟道掺杂区域包括第二导电类型杂质。

7. 发明申请

US20070278548A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20070278548A1
公开(公告)日：2007-12-06
申请号：US11769260
申请日：2007-06-27
申请人： Jin-Woo Lee , Cheol-Ju Yun , Hyeoung-Won Seo
发明人： Jin-Woo Lee , Cheol-Ju Yun , Hyeoung-Won Seo
IPC分类号： H01L27/108
CPC分类号： H01L27/10814 , H01L27/10823 , H01L27/10852 , H01L27/10873 , H01L27/10876 , H01L27/10885 , H01L27/10888 , H01L28/91 , H01L29/6659
摘要： A semiconductor device comprises a plurality of gate structures formed on a substrate, a gate spacer formed on a sidewall of the gate structures, a semiconductor pattern formed on the substrate between the gate structures, a first impurity region and a second impurity region formed in the semiconductor pattern and at surface portions of the substrate, respectively, wherein the first and second impurity regions include a first conductive type impurity, and a channel doping region surrounding the first impurity region, wherein the channel doping region includes a second conductive type impurity.
摘要翻译：半导体器件包括形成在衬底上的多个栅极结构，形成在栅极结构的侧壁上的栅极间隔物，形成在栅极结构之间的衬底上的半导体图案，形成在栅极结构中的第一杂质区域和第二杂质区域半导体图案和衬底的表面部分，其中第一和第二杂质区域包括第一导电类型杂质和围绕第一杂质区的沟道掺杂区域，其中沟道掺杂区域包括第二导电类型杂质。

8. 发明申请

US20070264769A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
公开(公告)号：US20070264769A1
公开(公告)日：2007-11-15
申请号：US11769287
申请日：2007-06-27
申请人： Jin-Woo Lee , Cheol-Ju Yun , Hyeoung-Won Seo
发明人： Jin-Woo Lee , Cheol-Ju Yun , Hyeoung-Won Seo
IPC分类号： H01L21/8242
CPC分类号： H01L27/10814 , H01L27/10823 , H01L27/10852 , H01L27/10873 , H01L27/10876 , H01L27/10885 , H01L27/10888 , H01L28/91 , H01L29/6659
摘要： A semiconductor device comprises a plurality of gate structures formed on a substrate, a gate spacer formed on a sidewall of the gate structures, a semiconductor pattern formed on the substrate between the gate structures, a first impurity region and a second impurity region formed in the semiconductor pattern and at surface portions of the substrate, respectively, wherein the first and second impurity regions include a first conductive type impurity, and a channel doping region surrounding the first impurity region, wherein the channel doping region includes a second conductive type impurity.

9. 发明申请

US20060006410A1 Semiconductor device and method of manufacturing the same 失效
公开(公告)号：US20060006410A1
公开(公告)日：2006-01-12
申请号：US11171710
申请日：2005-06-30
申请人： Jin-Woo Lee , Cheol-Ju Yun , Hyeoung-Won Seo
发明人： Jin-Woo Lee , Cheol-Ju Yun , Hyeoung-Won Seo
IPC分类号： H01L29/45
CPC分类号： H01L27/10814 , H01L27/10823 , H01L27/10852 , H01L27/10873 , H01L27/10876 , H01L27/10885 , H01L27/10888 , H01L28/91 , H01L29/6659
摘要： A semiconductor device comprises a plurality of gate structures formed on a substrate, a gate spacer formed on a sidewall of the gate structures, a semiconductor pattern formed on the substrate between the gate structures, a first impurity region and a second impurity region formed in the semiconductor pattern and at surface portions of the substrate, respectively, wherein the first and second impurity regions include a first conductive type impurity, and a channel doping region surrounding the first impurity region, wherein the channel doping region includes a second conductive type impurity.

10. 发明授权

US09468117B2 Memory device having heterogeneous terminals 有权
标题翻译：具有异构终端的存储器件
公开(公告)号：US09468117B2
公开(公告)日：2016-10-11
申请号：US14780716
申请日：2013-12-17
申请人： Jin-Woo Lee
发明人： Jin-Woo Lee
IPC分类号： G06F1/16 , H05K5/02 , H01R27/00 , H05K5/00 , H01R24/62
CPC分类号： H05K5/0278 , G06F1/1684 , H01R24/62 , H01R27/00 , H05K5/0004 , H05K5/0247
摘要： A memory device having heterogeneous terminals easily connects the memory device to a computer or a portable terminal without a specific gender. When a memory unit is connected to a computer, the memory unit slides out of the body and the first terminal of the memory unit is inserted into a USB connector of the computer, and when the memory unit is connected to a portable terminal, the connection unit slides out of the body and the second terminal of the connection unit is inserted in a mini-USB connector of the portable terminal, so it is possible to easily connect the memory unit to the portable terminal without a specific gender.
摘要翻译：具有异构终端的存储设备容易地将存储设备连接到计算机或便携式终端而不具有特定的性别。当存储器单元连接到计算机时，存储器单元从主体滑出并且存储器单元的第一端插入到计算机的USB连接器中，并且当存储器单元连接到便携式终端时，连接单元从主体滑出并且连接单元的第二端子插入便携式终端的mini-USB连接器中，因此可以容易地将存储器单元连接到便携式终端而没有特定的性别。

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