专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20100055831A1 PHASE CHANGEABLE MEMORY CELL ARRAY REGION AND METHOD OF FORMING THE SAME 有权
标题翻译：相变记忆体区域及其形成方法
公开(公告)号：US20100055831A1
公开(公告)日：2010-03-04
申请号：US12617782
申请日：2009-11-13
申请人： Hyeong-Geun An , Hideki Horii , Sang-Yeol Kang
发明人： Hyeong-Geun An , Hideki Horii , Sang-Yeol Kang
IPC分类号： H01L21/06
CPC分类号： H01L45/144 , H01L27/2436 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/1293 , H01L45/165 , H01L45/1666
摘要： A phase changeable memory cell array region includes a lower interlayer insulating layer disposed on a semiconductor substrate. The region also includes a plurality of conductive plugs disposed through the lower interlayer insulating layer. The region also includes a phase changeable material pattern operably disposed on the lower interlayer insulating layer, the phase changeable pattern covering at least two of the plurality of conductive plugs, wherein the phase changeable material pattern includes a plurality of first regions in contact with one or more of the plurality of conductive plugs and at least one second region interposed between the plurality of the first regions, wherein the at least one second region has a lower thermal conductivity than the plurality of first regions. The phase changeable memory cell array region also includes an upper interlayer insulating layer covering at least one of the phase changeable material pattern and the lower interlayer insulating layer. The region also includes conductive patterns disposed through the upper interlayer insulating layer and electrically connected to a plurality of predetermined regions of the plurality of first regions.
摘要翻译：相变存储单元阵列区域包括设置在半导体衬底上的下层间绝缘层。该区域还包括穿过下层间绝缘层设置的多个导电插塞。所述区域还包括可操作地设置在所述下层间绝缘层上的可相变材料图案，所述相变图案覆盖所述多个导电插塞中的至少两个，其中所述相变材料图案包括多个与第多个导电插塞中的多个和插入在多个第一区域之间的至少一个第二区域，其中至少一个第二区域具有比多个第一区域更低的热导率。相变存储单元阵列区域还包括覆盖相变材料图案和下层间绝缘层中的至少一个的上层间绝缘层。该区域还包括通过上层间绝缘层设置并电连接到多个第一区域中的多个预定区域的导电图案。

2. 发明授权

US07638787B2 Phase changeable memory cell array region and method of forming the same 有权
标题翻译：相变存储单元阵列区域及其形成方法
公开(公告)号：US07638787B2
公开(公告)日：2009-12-29
申请号：US11581012
申请日：2006-10-16
申请人： Hyeong-Geun An , Hideki Horii , Sang-Yeol Kang
发明人： Hyeong-Geun An , Hideki Horii , Sang-Yeol Kang
IPC分类号： H01L29/02 , G11C11/00
CPC分类号： H01L45/144 , H01L27/2436 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/1293 , H01L45/165 , H01L45/1666
摘要： A phase changeable memory cell array region includes a lower interlayer insulating layer disposed on a semiconductor substrate. The region also includes a plurality of conductive plugs disposed through the lower interlayer insulating layer. The region also includes a phase changeable material pattern operably disposed on the lower interlayer insulating layer, the phase changeable pattern covering at least two of the plurality of conductive plugs, wherein the phase changeable material pattern includes a plurality of first regions in contact with one or more of the plurality of conductive plugs and at least one second region interposed between the plurality of the first regions, wherein the at least one second region has a lower thermal conductivity than the plurality of first regions. The phase changeable memory cell array region also includes an upper interlayer insulating layer covering at least one of the phase changeable material pattern and the lower interlayer insulating layer. The region also includes conductive patterns disposed through the upper interlayer insulating layer and electrically connected to a plurality of predetermined regions of the plurality of first regions.
摘要翻译：相变存储单元阵列区域包括设置在半导体衬底上的下层间绝缘层。该区域还包括穿过下层间绝缘层设置的多个导电插塞。所述区域还包括可操作地设置在所述下层间绝缘层上的可相变材料图案，所述相变图案覆盖所述多个导电插塞中的至少两个，其中所述相变材料图案包括多个与第多个导电插塞中的多个和插入在多个第一区域之间的至少一个第二区域，其中至少一个第二区域具有比多个第一区域更低的热导率。相变存储单元阵列区域还包括覆盖相变材料图案和下层间绝缘层中的至少一个的上层间绝缘层。该区域还包括通过上层间绝缘层设置并电连接到多个第一区域中的多个预定区域的导电图案。

3. 发明申请

US20070111440A1 Phase changeable memory cell array region and method of forming the same 有权
标题翻译：相变存储单元阵列区域及其形成方法
公开(公告)号：US20070111440A1
公开(公告)日：2007-05-17
申请号：US11581012
申请日：2006-10-16
申请人： Hyeong-Geun An , Hideki Horii , Sang-Yeol Kang
发明人： Hyeong-Geun An , Hideki Horii , Sang-Yeol Kang
IPC分类号： H01L21/00 , H01L21/336 , H01L29/94
CPC分类号： H01L45/144 , H01L27/2436 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/1293 , H01L45/165 , H01L45/1666
摘要： A phase changeable memory cell array region includes a lower interlayer insulating layer disposed on a semiconductor substrate. The region also includes a plurality of conductive plugs disposed through the lower interlayer insulating layer. The region also includes a phase changeable material pattern operably disposed on the lower interlayer insulating layer, the phase changeable pattern covering at least two of the plurality of conductive plugs, wherein the phase changeable material pattern includes a plurality of first regions in contact with one or more of the plurality of conductive plugs and at least one second region interposed between the plurality of the first regions, wherein the at least one second region has a lower thermal conductivity than the plurality of first regions. The phase changeable memory cell array region also includes an upper interlayer insulating layer covering at least one of the phase changeable material pattern and the lower interlayer insulating layer. The region also includes conductive patterns disposed through the upper interlayer insulating layer and electrically connected to a plurality of predetermined regions of the plurality of first regions.
摘要翻译：相变存储单元阵列区域包括设置在半导体衬底上的下层间绝缘层。该区域还包括穿过下层间绝缘层设置的多个导电插塞。所述区域还包括可操作地设置在所述下层间绝缘层上的可相变材料图案，所述相变图案覆盖所述多个导电插塞中的至少两个，其中所述相变材料图案包括多个与第多个导电插塞中的多个和插入在多个第一区域之间的至少一个第二区域，其中至少一个第二区域具有比多个第一区域更低的热导率。相变存储单元阵列区域还包括覆盖相变材料图案和下层间绝缘层中的至少一个的上层间绝缘层。该区域还包括通过上层间绝缘层设置并电连接到多个第一区域中的多个预定区域的导电图案。

4. 发明授权

US08039298B2 Phase changeable memory cell array region and method of forming the same 有权
标题翻译：相变存储单元阵列区域及其形成方法
公开(公告)号：US08039298B2
公开(公告)日：2011-10-18
申请号：US12617782
申请日：2009-11-13
申请人： Hyeong-Geun An , Hideki Horii , Sang-Yeol Kang
发明人： Hyeong-Geun An , Hideki Horii , Sang-Yeol Kang
IPC分类号： H01L21/06 , H01L21/00 , G11C11/00
CPC分类号： H01L45/144 , H01L27/2436 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/1293 , H01L45/165 , H01L45/1666
摘要： A phase changeable memory cell array region includes a lower interlayer insulating layer disposed on a semiconductor substrate. The region also includes a plurality of conductive plugs disposed through the lower interlayer insulating layer. The region also includes a phase changeable material pattern operably disposed on the lower interlayer insulating layer, the phase changeable pattern covering at least two of the plurality of conductive plugs, wherein the phase changeable material pattern includes a plurality of first regions in contact with one or more of the plurality of conductive plugs and at least one second region interposed between the plurality of the first regions, wherein the at least one second region has a lower thermal conductivity than the plurality of first regions. The phase changeable memory cell array region also includes an upper interlayer insulating layer covering at least one of the phase changeable material pattern and the lower interlayer insulating layer. The region also includes conductive patterns disposed through the upper interlayer insulating layer and electrically connected to a plurality of predetermined regions of the plurality of first regions.
摘要翻译：相变存储单元阵列区域包括设置在半导体衬底上的下层间绝缘层。该区域还包括穿过下层间绝缘层设置的多个导电插塞。所述区域还包括可操作地设置在所述下层间绝缘层上的可相变材料图案，所述相变图案覆盖所述多个导电插塞中的至少两个，其中所述相变材料图案包括多个与第多个导电插塞中的多个和插入在多个第一区域之间的至少一个第二区域，其中至少一个第二区域具有比多个第一区域更低的热导率。相变存储单元阵列区域还包括覆盖相变材料图案和下层间绝缘层中的至少一个的上层间绝缘层。该区域还包括通过上层间绝缘层设置并电连接到多个第一区域中的多个预定区域的导电图案。

5. 发明授权

US08685494B2 ALD method of forming thin film comprising a metal 有权
标题翻译：形成包含金属的薄膜的ALD方法
公开(公告)号：US08685494B2
公开(公告)日：2014-04-01
申请号：US13242037
申请日：2011-09-23
申请人： Jae-Soon Lim , Jae-Hyoung Choi , Youn-Soo Kim , Min-Young Park , Sang-Yeol Kang
发明人： Jae-Soon Lim , Jae-Hyoung Choi , Youn-Soo Kim , Min-Young Park , Sang-Yeol Kang
IPC分类号： C23C16/00
CPC分类号： C23C16/34 , C23C16/45525
摘要： A method of forming a metal thin film can reduce leakage current while improving electric properties by improving step coverage of a device. The method of forming a metal thin film includes supplying a metal precursor including chlorine, purging byproducts produced after the supplying of the metal precursor by injecting a purge gas, supplying a reactant to allow the reactant and the metal precursor to react with each other to form a thin film layer, and purging the byproducts produced after the reaction by injecting a purge gas, wherein before the supplying of the metal precursor, the method further includes supplying a reactant to be adsorbed on a treated product.
摘要翻译：形成金属薄膜的方法可以通过提高器件的台阶覆盖率来改善电性能来减少漏电流。形成金属薄膜的方法包括：供给包含氯的金属前体，通过注入吹扫气体，在供给金属前体之后产生的副产物，供应反应物以允许反应物和金属前体彼此反应形成薄膜层，并且通过注入吹扫气体来净化反应后产生的副产物，其中在供给金属前体之前，所述方法还包括供给被处理产物上被吸附的反应物。

6. 发明授权

US08339765B2 Capacitor 有权
标题翻译：电容器
公开(公告)号：US08339765B2
公开(公告)日：2012-12-25
申请号：US12628598
申请日：2009-12-01
申请人： Hoon-Sang Choi , Ki-Vin Im , Se-Hoon Oh , Sang-Yeol Kang , Cha-Young Yoo
发明人： Hoon-Sang Choi , Ki-Vin Im , Se-Hoon Oh , Sang-Yeol Kang , Cha-Young Yoo
IPC分类号： H01G4/30
CPC分类号： H01G4/33 , H01G4/01 , H01L27/10817 , H01L27/10852 , H01L28/91
摘要： A capacitor includes a substrate, a plurality of first storage electrodes, a plurality of second storage electrodes, a first supporting layer pattern, a dielectric layer and a plate electrode. A plurality of contact pads is formed I the substrate. The first storage electrodes are arranged along lines parallel with a first direction and electrically connected to the contact pads, respectively. The second storage electrodes are respectively stacked on the first storage electrodes. The first supporting layer pattern extends in a direction parallel with the first direction between adjacent second storage electrodes and makes contact with the adjacent second storage electrodes to support the second storage electrodes. The dielectric layer is formed on the first and second storage electrodes. The plate electrode is formed on the dielectric layer.
摘要翻译：电容器包括基板，多个第一存储电极，多个第二存储电极，第一支撑层图案，电介质层和平板电极。在基板上形成多个接触焊盘。第一存储电极沿着与第一方向平行的线分别布置并且电连接到接触垫。第二存储电极分别堆叠在第一存储电极上。第一支撑层图案在与相邻的第二存储电极之间的第一方向平行的方向上延伸，并与相邻的第二存储电极接触以支撑第二存储电极。介电层形成在第一和第二存储电极上。在电介质层上形成平板电极。

7. 发明授权

US09349583B2 Method of fabricating semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US09349583B2
公开(公告)日：2016-05-24
申请号：US13775595
申请日：2013-02-25
申请人： Min-Young Park , Youn-Soo Kim , Sang-Yeol Kang , Cha-Young Yoo , Jae-Soon Lim , Jae-Hyoung Choi
发明人： Min-Young Park , Youn-Soo Kim , Sang-Yeol Kang , Cha-Young Yoo , Jae-Soon Lim , Jae-Hyoung Choi
IPC分类号： H01L21/02 , C23C16/04 , C23C16/40 , C23C16/455 , H01L21/28 , H01L49/02
CPC分类号： H01L21/02104 , C23C16/045 , C23C16/405 , C23C16/45527 , H01L21/28282 , H01L28/40
摘要： Methods of fabricating a semiconductor device include forming a deposited film on a semiconductor substrate in a process chamber by repeatedly forming unit layers on the semiconductor substrate. The unit layer is formed by forming a preliminary unit layer on the semiconductor substrate by supplying a process material including a precursor material and film-control material into the process chamber, purging the process chamber, forming a unit layer from the preliminary unit layer, and again purging the process chamber. The precursor material includes a central atom and a ligand bonded to the central atom, and the film-control material includes a hydride of the ligand.
摘要翻译：制造半导体器件的方法包括通过在半导体衬底上重复形成单位层，在处理室中的半导体衬底上形成沉积膜。单元层通过在半导体基板上形成预备单元层而形成，该方法是将包括前体材料和薄膜控制材料的处理材料供给到处理室中，从处理室中清除处理室，从预备单元层形成单元层，以及再次清洗处理室。前体材料包括中心原子和与中心原子键合的配体，膜控制材料包括配体的氢化物。

8. 发明申请

US20120094022A1 METHOD OF FORMING METAL THIN FILM 有权
标题翻译：形成金属薄膜的方法
公开(公告)号：US20120094022A1
公开(公告)日：2012-04-19
申请号：US13242037
申请日：2011-09-23
申请人： Jae-Soon Lim , Jae-Hyoung Choi , Youn-Soo Kim , Min-Young Park , Sang-Yeol Kang
发明人： Jae-Soon Lim , Jae-Hyoung Choi , Youn-Soo Kim , Min-Young Park , Sang-Yeol Kang
IPC分类号： C23C16/06 , C23C16/44
CPC分类号： C23C16/34 , C23C16/45525
摘要： Provided is a method of forming a metal thin film which can reduce leakage current while improving electric properties by improving step coverage of a device. The method of forming a metal thin film includes supplying a metal precursor including chlorine, purging byproducts produced after the supplying of the metal precursor by injecting a purge gas, supplying a reactant to allow the reactant and the metal precursor to react with each other to form a thin film layer, and purging the byproducts produced after the reaction by injecting a purge gas, wherein before the supplying of the metal precursor, the method further includes supplying a reactant to be adsorbed on a treated product.
摘要翻译：提供一种形成金属薄膜的方法，其可以通过改善器件的台阶覆盖而改善电特性，从而降低漏电流。形成金属薄膜的方法包括：供给包含氯的金属前体，通过注入吹扫气体，在供给金属前体之后产生的副产物，供应反应物以允许反应物和金属前体彼此反应形成薄膜层，并且通过注入吹扫气体来净化反应后产生的副产物，其中在供给金属前体之前，所述方法还包括供给被处理产物上被吸附的反应物。

9. 发明申请

US20110136317A1 Semiconductor device, method of fabricating the same, and semicondutor module, electronic circuit board, and electronic system including the device 审中-公开
标题翻译：半导体装置及其制造方法，半导体模块，电子电路板以及包括该装置的电子系统
公开(公告)号：US20110136317A1
公开(公告)日：2011-06-09
申请号：US12659830
申请日：2010-03-23
申请人： Sang-Yeol Kang , Youn-Soo Kim , Jae-Hyoung Choi , Jae-Soon Lim , Min-Young Park , Suk-Jin Chung
发明人： Sang-Yeol Kang , Youn-Soo Kim , Jae-Hyoung Choi , Jae-Soon Lim , Min-Young Park , Suk-Jin Chung
IPC分类号： H01L21/02
CPC分类号： H01L28/40 , H01L21/02183 , H01L21/02189 , H01L21/02194 , H01L21/022 , H01L21/0228 , H01L27/10852 , H01L29/40114
摘要： Example embodiments relate to a semiconductor device including an oxide dielectric layer and a non-oxide dielectric layer, a method of fabricating the device, and a semiconductor module, an electronic circuit board, and an electronic system including the device. The semiconductor device may include a lower electrode, an oxide dielectric layer disposed on the lower electrode, a non-oxide dielectric layer disposed on the oxide dielectric layer, and an upper electrode disposed on the non-oxide dielectric layer.
摘要翻译：示例性实施例涉及包括氧化物介电层和非氧化物介电层的半导体器件，制造器件的方法，以及包括该器件的半导体模块，电子电路板和电子系统。半导体器件可以包括下电极，设置在下电极上的氧化物介电层，设置在氧化物电介质层上的非氧化物介电层，以及设置在非氧化物介电层上的上电极。

10. 发明授权

US09412583B2 Methods of forming dielectric layers and methods of manufacturing semiconductor devices using the same 有权
标题翻译：形成电介质层的方法和使用其制造半导体器件的方法
公开(公告)号：US09412583B2
公开(公告)日：2016-08-09
申请号：US13400952
申请日：2012-02-21
申请人： Sang-Yeol Kang , Suk-Jin Chung , Youn-Soo Kim , Jae-Hyoung Choi , Jae-Soon Lim , Min-Young Park
发明人： Sang-Yeol Kang , Suk-Jin Chung , Youn-Soo Kim , Jae-Hyoung Choi , Jae-Soon Lim , Min-Young Park
IPC分类号： H01L21/28 , H01L21/02 , H01L29/51 , H01L27/108 , H01L49/02 , H01L29/78
CPC分类号： H01L28/60 , H01L21/02178 , H01L21/02181 , H01L21/02189 , H01L21/02271 , H01L21/0228 , H01L21/28194 , H01L27/10808 , H01L27/10814 , H01L27/10855 , H01L28/40 , H01L29/517 , H01L29/78
摘要： To form a dielectric layer, an organometallic precursor is adsorbed on a substrate loaded into a process chamber. The organometallic precursor includes a central metal and ligands bound to the central metal. An inactive oxidant is provided onto the substrate. The inactive oxidant is reactive with the organometallic precursor. An active oxidant is also provided onto the substrate. The active oxidant has a higher reactivity than that of the inactive oxidant.
摘要翻译：为了形成电介质层，有机金属前体被吸附在装载到处理室中的基板上。有机金属前体包括中心金属和与中心金属结合的配体。在基材上提供无活性氧化剂。无活性氧化剂与有机金属前体反应。活性氧化剂也提供到基底上。活性氧化剂的反应活性高于非活性氧化剂。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式