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1. 发明授权

US4893306A Method and apparatus for multiplexing circuit and packet traffic 失效
标题翻译：电路和数据包流量复用的方法和装置
公开(公告)号：US4893306A
公开(公告)日：1990-01-09
申请号：US118977
申请日：1987-11-10
申请人： Hung-Hsiang J. Chao , Sang H. Lee , Liang T. Wu
发明人： Hung-Hsiang J. Chao , Sang H. Lee , Liang T. Wu
IPC分类号： H04J3/16 , H04J3/24
CPC分类号： H04J3/1682 , H04J3/247
摘要： A data transmission technique referred to herein as Dynamic Time Division Multiplexing (DTDM) is disclosed along with a set of multiplexers and demultiplexers required to apply DTDM in an actual telecommunications network. The DTDM technique uses a transmission format which is compatible with the existing digital circuit transmission format and the packet transmission format so that DTDM is able to handle the transmission of circuit and packet traffic. Thus, DTDM provides a flexible migration strategy between present circuit networks and future broadband packet networks.
摘要翻译：本文中称为动态时分复用（DTDM）的数据传输技术与在实际电信网络中应用DTDM所需的一组复用器和解复用器一起被公开。 DTDM技术使用与现有数字电路传输格式和分组传输格式兼容的传输格式，使得DTDM能够处理电路和分组业务的传输。因此，DTDM在当前的电路网络和未来的宽带分组网络之间提供灵活的迁移策略。

2. 发明授权

US4833673A Time division multiplexer for DTDM bit streams 失效
标题翻译：用于DTDM比特流的时分复用器
公开(公告)号：US4833673A
公开(公告)日：1989-05-23
申请号：US118978
申请日：1987-11-10
申请人： Hung-Hsiang J. Chao , Sang H. Lee
发明人： Hung-Hsiang J. Chao , Sang H. Lee
IPC分类号： H04J3/16 , H04J3/24
CPC分类号： H04J3/247 , H04J3/1682
摘要： A multiplexer for time division multiplexing a plurality of DTDM bit streams is disclosed. By taking advantage of the fact that the frames comprising each DTDM bit stream are not 100% occupied, the frequency of the higher speed output bit stream can be made equal to the product of the nominal center frequency of the input tributaries and the number of input tributaries. This is accomplished through the positive and negative stuffing of DTDM frames.
摘要翻译：公开了一种用于时分复用多个DTDM比特流的多路复用器。通过利用包括每个DTDM比特流的帧不被100％占用的事实，可以使高速输出比特流的频率等于输入支路的标称中心频率与输入数量的乘积支流。这是通过DTDM帧的正负填充来实现的。

3. 发明授权

US5079763A Customer premises network node access protocol 失效
标题翻译：客户端网络节点访问协议
公开(公告)号：US5079763A
公开(公告)日：1992-01-07
申请号：US662123
申请日：1991-02-28
申请人： Hung-Hsiang J. Chao , Gennady Shtirmer , Lanny S. Smoot
发明人： Hung-Hsiang J. Chao , Gennady Shtirmer , Lanny S. Smoot
IPC分类号： H04J3/06 , H04L12/28 , H04L12/56 , H04Q11/04
CPC分类号： H04L12/2852 , H04J3/0632 , H04Q11/0478 , H04L2012/5614
摘要： A method of controlling the access of a plurality of nodes to a bus which interconnects the nodes in a daisy chain. The method enables each node in the network to keep track of the transmission requests of all other nodes. Each node will compare it's needs against all requests and will only transmit onto the network after it has let pass sufficient resources to satisfy the downstream nodes.
摘要翻译：控制多个节点对连接菊花链中的节点的总线的访问的方法。该方法使得网络中的每个节点能够跟踪所有其他节点的传输请求。每个节点将根据所有请求进行比较，只有在传递足够的资源以满足下游节点之后，才能将其传输到网络上。

4. 发明授权

US5278828A Method and system for managing queued cells 失效
标题翻译：用于管理排队的单元的方法和系统
公开(公告)号：US5278828A
公开(公告)日：1994-01-11
申请号：US893265
申请日：1992-06-04
申请人： Hung-Hsiang J. Chao
发明人： Hung-Hsiang J. Chao
IPC分类号： H04L12/56 , H04Q11/04 , H04J3/26
CPC分类号： H04L49/30 , H04L49/20 , H04L49/3081 , H04L49/508 , H04Q11/0478 , H04L2012/5651 , H04L2012/5672 , H04L2012/5681 , H04L49/103
摘要： A queue management method and system manages queued cells in such a way that higher priority cells are always served first, the low priority cells are dropped when the queue is full and, within the same priority, any interference is prevented. Four different architecture designs for such queue management are presented and their implementation feasibility and hardware complexity are compared and contrasted. A departure sequence is assigned to each cell in the novel architecture to implement the queue management. The sequence applies the concepts of fully distributed and highly parallel processing to schedule cell sending or dropping sequences. Preferably, a sequencer is provided such that the queue size and the number of priority levels can grow flexibly and without limit.
摘要翻译：队列管理方法和系统以这样的方式管理排队的小区，使得始终首先服务较高优先级的小区，当队列满时，低优先级小区被丢弃，并且在相同的优先级内，防止任何干扰。介绍了这种队列管理的四种不同架构设计，并对其实现可行性和硬件复杂性进行了比较和对比。出发序列被分配给新颖架构中的每个小区以实现队列管理。该序列应用完全分布和高度并行处理的概念来调度信元发送或丢弃序列。优选地，提供定序器，使得队列大小和优先级数量可以灵活地且无限制地增长。

5. 发明授权

US5179552A Crosspoint matrix switching element for a packet switch 失效
标题翻译：用于分组交换的交叉点矩阵切换元件
公开(公告)号：US5179552A
公开(公告)日：1993-01-12
申请号：US821264
申请日：1992-01-10
申请人： Hung-Hsiang J. Chao
发明人： Hung-Hsiang J. Chao
IPC分类号： H04J3/24 , H04L12/56 , H04Q11/04
CPC分类号： H04L12/5601 , H04J3/247 , H04L49/106 , H04L49/1553 , H04L49/1576 , H04L49/1584 , H04L49/258 , H04Q11/0478 , H04L2012/5627 , H04L2012/5647 , H04L2012/5651
摘要： A crosspoint matrix switching element and associated method for a large (e.g. approximately 1 Terabit/second) packet switch (200) or a non-buffer based statistical multiplexor (1810), using a crossbar matrix network in which, first, the output ports of individual switching elements (e.g. 1340.sub.1,1, 1340.sub.2,1) are partitioned into various groups (e.g. 1110) in order to share routing paths (links) (e.g. 1115.sub.1, 1115.sub.2, . . . , 1115.sub.K) among the elements in any such group and, second, the outputs of each such group are themselves recursively partitioned into a succession of serially connected groups (e.g. 1140, 1160) that each provides a decreasing number of outputs until one such output is provided for each corresponding output port (278.sub.1, 278.sub.2, . . . , 278.sub.N) of the switch. The switching element includes a control circuit which compares corresponding bits of two incoming bit streams in specific time windows to generate control signals and a routing circuit responsive to the control signals for routing the two input bit streams alternatively to two data outputs.
摘要翻译：一种用于大（例如大约1兆位/秒）分组交换机（200）或非基于缓冲器的统计多路复用器（1810）的交叉点矩阵切换元件和相关方法，其使用交叉矩阵网络，其中，首先输出端口各个开关元件（例如13401,1，13402,1）被划分成各种组（例如1110），以便在任何这样的组中的元件之间共享路由路径（链路）（例如，11151,11152，...，1115K）并且其次，每个这样的组的输出本身被递归地划分成一系列串行连接的组（例如1140,1160），每个组提供递减数量的输出，直到为每个对应的输出端口提供一个这样的输出（2781,2782 ，...，278N）。开关元件包括控制电路，其比较特定时间窗口中的两个输入比特流的相应比特以产生控制信号，以及响应于用于将两个输入比特流路由到两个数据输出的控制信号的路由电路。

6. 发明授权

US5050164A Optical customer premises network 失效
标题翻译：光客户驻地网
公开(公告)号：US5050164A
公开(公告)日：1991-09-17
申请号：US429845
申请日：1989-10-31
申请人： Hung-Hsiang J. Chao , Gennady Shtirmer , Lanny S. Smoot
发明人： Hung-Hsiang J. Chao , Gennady Shtirmer , Lanny S. Smoot
IPC分类号： H04J3/06 , H04L12/28 , H04L12/56 , H04Q11/04
CPC分类号： H04L12/2852 , H04J3/0632 , H04Q11/0478 , H04L2012/5614
摘要： A customer premises network for interfacing customer premises equipment with a broadband digital trunk and exchange network comprises a relatively large bandwidth optical broadcast bus for broadcasting downstream data to the customer premises equipment and a smaller bandwidth looped bus for transmitting upstream data from the customer premises equipment. The units of customer premises equipment are connected by the looped bus in a daisy chain.
摘要翻译：用于将客户驻地设备与宽带数字中继线和交换网络连接的用户驻地网络包括用于向用户驻地设备广播下游数据的较大带宽光学广播总线和用于从客户驻地设备发送上行数据的较小带宽循环总线。客户端设备的单元通过环形总线以菊花链连接。

7. 发明授权

US5197064A Distributed modular packet switch employing recursive partitioning 失效
标题翻译：分布式模块化分组交换机采用递归分区
公开(公告)号：US5197064A
公开(公告)日：1993-03-23
申请号：US618119
申请日：1990-11-26
申请人： Hung-Hsiang J. Chao
发明人： Hung-Hsiang J. Chao
IPC分类号： H04J3/24 , H04L12/56 , H04Q11/04
CPC分类号： H04L12/5601 , H04J3/247 , H04L49/1576 , H04L49/1584 , H04L49/258 , H04Q11/0478 , H04L2012/5647 , H04L2012/5651 , H04L2012/5652 , H04L2012/5681
摘要： Apparatus, and accompanying methods for use therein, for illustratively implementing a large (e.g. approximately 1 Terabit/second) packet switch (200) or a non-buffer based statistical multiplexor (1810), using a crossbar matrix network in which, first, the output ports of individual switching elements (e.g. 1340.sub.1,1, 1340.sub.2,1) are partitioned into various groups (e.g. 1110) in order to share routing paths (links) (e.g. 1115.sub.1, 1115.sub.2, . . . , 1115.sub.K) among the elements in any such group and, second, the outputs of each such group are themselves recursively partitioned into a succession of serially connected groups (e.g. 1140, 1160) that each provides a decreasing number of outputs until one such output is provided for each corresponding output port (278.sub.1, 278.sub.2, . . . , 278.sub.N) of the switch. Such a switch also utilizes channel grouping to improve overall performance and a crossbar switching fabric that internally distributes contention resolution and filtering functions among the individual switching elements themselves to reduce complexity, provide modularity, reduce growth limitations and relax synchronization requirements of the entire switch.
摘要翻译：装置及其使用的方法，用于示意性地使用交叉矩阵网络来实现大（例如大约1兆比特/秒）分组交换机（200）或非基于缓冲器的统计多路复用器（1810），其中，首先，各个开关元件（例如，13401,1,13402,1）的输出端口被划分成各种组（例如，1110），以便共享各个元件之间的路由路径（链路）（例如，11151,11152，...，1115K）任何这样的组，并且其次，每个这样的组的输出本身被递归地划分成一系列串行连接的组（例如1140,1160），每个组提供递减数量的输出，直到为每个对应的输出端口提供一个这样的输出（ 2781,2782，... 278N）。这样的交换机还利用信道分组来提高总体性能，并且在各个交换单元本身内部分配争用解决和过滤功能的交叉交换结构以降低复杂性，提供模块化，减少增长限制并且放松整个交换机的同步要求。

8. 发明授权

US5124978A Grouping network based non-buffer statistical multiplexor 失效
标题翻译：分组网络非缓冲区统计多路复用器
公开(公告)号：US5124978A
公开(公告)日：1992-06-23
申请号：US637230
申请日：1991-01-03
申请人： Hung-Hsiang J. Chao
发明人： Hung-Hsiang J. Chao
IPC分类号： H04J3/24 , H04L12/56 , H04Q11/04
CPC分类号： H04L12/5601 , H04J3/247 , H04L49/1576 , H04L49/1584 , H04L49/258 , H04L49/455 , H04Q11/0478 , H04L2012/5647 , H04L2012/5651 , H04L2012/5674 , H04L2012/5681
摘要： Apparatus, and accompanying methods for use therein, for illustratively implementing a large (e.g. approximately 1 Terabit/second) packet switch (200) or a non-buffer based statistical multiplexor (1810), using a crossbar matrix network in which, first, the output ports of individual switching elements (e.g. 1340.sub.1,1, 1340.sub.2,1) are partitioned into various groups (e.g. 1110) in order to share routing paths (links) (e.g. 1115.sub.1, 1115.sub.2, . . . , 1115.sub.K) among the elements in any such group and, second, the outputs of each such group are themselves recursively partitioned into a succession of serially connected groups (e.g. 1140, 1160) that each provides a decreasing number of outputs until one such output is provided for each corresponding output port (278.sub.1, 278.sub.2, . . . , 278.sub.N) of the switch. Such a switch also utilizes channel grouping to improve overall performance and a crossbar switching fabric that internally distributes contention resolution and filtering functions among the individual switching elements themselves to reduce complexity, provide modularity, reduce growth limitations and relax synchronization requirements of the entire switch.
摘要翻译：装置及其使用的方法，用于示意性地使用交叉矩阵网络来实现大（例如大约1兆比特/秒）分组交换机（200）或非基于缓冲器的统计多路复用器（1810），其中，首先，各个开关元件（例如，13401,1,13402,1）的输出端口被划分成各种组（例如，1110），以便共享各个元件之间的路由路径（链路）（例如，11151,11152，...，1115K）任何这样的组，并且其次，每个这样的组的输出本身被递归地划分成一系列串行连接的组（例如1140,1160），每个组提供递减数量的输出，直到为每个对应的输出端口提供一个这样的输出（ 2781,2782，... 278N）。这样的交换机还利用信道分组来提高总体性能，并且在各个交换单元本身内部分配争用解决和过滤功能的交叉交换结构以降低复杂性，提供模块化，减少增长限制并且放松整个交换机的同步要求。

9. 发明授权

US4819226A Framer circuit for use in a DTDM network 失效
标题翻译：用于DTDM网络的成帧器电路
公开(公告)号：US4819226A
公开(公告)日：1989-04-04
申请号：US118898
申请日：1987-11-10
申请人： Mark W. Beckner , Hung-Hsiang J. Chao , Thomas J. Robe , Lanny S. Smoot
发明人： Mark W. Beckner , Hung-Hsiang J. Chao , Thomas J. Robe , Lanny S. Smoot
IPC分类号： H04J3/16 , H04J3/24 , H04J3/02
CPC分类号： H04J3/1682 , H04J3/247
摘要： A framer circuit which may be implemented as a single chip is disclosed. The framer circuit performs a number of functions in a DTDM network including generating trains of empty DTDM frames, enabling the writing of data packets into specific DTDM frames and the examination of header data in specific DTDM frames to generate signals for the control of peripheral circuits. The framer circuit comprises an input serial/parallel converter, a frame detection circuit, an output parallel/serial converter and a control unit comprising one or more finite state machines for generating proper control signals such as read and write strobes for data insertion and extraction.
摘要翻译：可以实现为单个芯片的成帧器电路被公开。成帧器电路在DTDM网络中执行多个功能，包括生成空DTDM帧的列，使得能够将数据分组写入特定的DTDM帧中，并且检查特定DTDM帧中的报头数据以产生用于外围电路控制的信号。成帧器电路包括输入串行/并行转换器，帧检测电路，输出并行/串行转换器和包括一个或多个有限状态机的控制单元，用于产生用于数据插入和提取的适当的控制信号，例如读和写选通。

10. 发明授权

US5381407A Method and system for controlling user traffic to a fast packet switching system 失效
标题翻译：用于控制快速分组交换系统的用户流量的方法和系统
公开(公告)号：US5381407A
公开(公告)日：1995-01-10
申请号：US893274
申请日：1992-06-04
申请人： Hung-Hsiang J. Chao
发明人： Hung-Hsiang J. Chao
IPC分类号： H04L12/56 , H04Q11/04 , H04J3/14
CPC分类号： H04L12/5602 , H04Q11/0478 , H04L2012/5636 , H04L2012/5637 , H04L2012/5651
摘要： A method and system are provided for controlling user traffic to a fast packet switching system using the leaky bucket scheme. Each of the packets (53 byte length cell) originates at a source of packets and has a virtual channel identifier (VCI). The method includes the step of receiving the packets, each of the packets having associated therewith an arrival time. The packets are stored at an addressable location in a first memory. The first memory having a plurality of addressable locations. In a second memory, there are stored addresses corresponding to the addressable locations in the first memory in which a packet is not yet stored. The addresses stored in the second memory are utilized in the step of storing the received packets. A credit manager circuit determines whether a stored packet complies with predetermined traffic parameters such as average arrival rate and maximum burst rate. This determination is based on a packet's arrival time and its VCI to obtain a validated packet. The credit manager circuit retrieves the validated packet from the first memory and the retrieved packet is then transmitted to the packet switching system.
摘要翻译：提供了一种方法和系统，用于控制使用泄漏桶方案的快速分组交换系统的用户流量。每个分组（53字节长度小区）起始于分组的源，并且具有虚拟信道标识符（VCI）。该方法包括接收分组的步骤，每个分组具有相关联的到达时间。分组被存储在第一存储器中的可寻址位置。第一存储器具有多个可寻址位置。在第二存储器中，存储对应于第一存储器中的可寻址位置的地址，其中分组尚未被存储。存储在第二存储器中的地址在存储接收到的分组的步骤中被使用。信用管理器电路确定存储的分组是否符合预定的业务参数，例如平均到达速率和最大突发速率。该确定基于分组的到达时间和其VCI来获得经验证的分组。信用管理电路从第一个存储器检索经过验证的数据包，然后将检索的数据包发送到数据包交换系统。

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