会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 1. 发明授权
    • High write and erase efficiency embedded flash cell
    • 高写入和擦除效率嵌入式闪存单元
    • US07557402B2
    • 2009-07-07
    • US11599930
    • 2006-11-15
    • Der-Shin ShyuHung-Cheng SungChen-Ming Huang
    • Der-Shin ShyuHung-Cheng SungChen-Ming Huang
    • H01L29/34
    • H01L27/11521H01L27/115H01L29/42324H01L29/7885
    • An embedded flash cell structure comprising a structure, a first floating gate having an exposed side wall over the structure, a second floating gate having an exposed side wall over the structure and spaced apart from the first floating gate, a first pair of spacers over the respective first floating gate and the second floating gate, a second pair of spacers at least over the respective exposed side walls of the first and second floating gates, a source area in the structure between the second pair of spacers, a plug over the source implant, and first and second control gates outboard of the first pair of spacers and exposing outboard portions of the structure and respective drain areas in the exposed outboard portions of the structure is provided. A method of forming the embedded flash cell structure is also provided.
    • 一种嵌入式闪存单元结构,其包括结构,第一浮动栅极,其具有在所述结构上方的暴露侧壁,第二浮动栅极,具有在所述结构上并与所述第一浮动栅极间隔开的暴露的侧壁; 相应的第一浮动栅极和第二浮动栅极,至少在第一和第二浮动栅极的相应暴露的侧壁上方的第二对间隔物,在第二对间隔物之间​​的结构中的源极区域,源极植入物 并且设置在第一对间隔件外侧的第一和第二控制门,并且暴露在结构的暴露的外侧部分中的结构的外侧部分和相应的漏极区域。 还提供了一种形成嵌入式闪存单元结构的方法。
    • 2. 发明申请
    • High write and erase efficiency embedded flash cell
    • 高写入和擦除效率嵌入式闪存单元
    • US20070063248A1
    • 2007-03-22
    • US11599930
    • 2006-11-15
    • Der-Shin ShyuHung-Cheng SungChen-Ming Huang
    • Der-Shin ShyuHung-Cheng SungChen-Ming Huang
    • H01L29/76
    • H01L27/11521H01L27/115H01L29/42324H01L29/7885
    • An embedded flash cell structure comprising a structure, a first floating gate having an exposed side wall over the structure, a second floating gate having an exposed side wall over the structure and spaced apart from the first floating gate, a first pair of spacers over the respective first floating gate and the second floating gate, a second pair of spacers at least over the respective exposed side walls of the first and second floating gates, a source area in the structure between the second pair of spacers, a plug over the source implant, and first and second control gates outboard of the first pair of spacers and exposing outboard portions of the structure and respective drain areas in the exposed outboard portions of the structure is provided. A method of forming the embedded flash cell structure is also provided.
    • 一种嵌入式闪存单元结构,其包括结构,第一浮动栅极,其具有在所述结构上方的暴露侧壁,第二浮动栅极,具有在所述结构上并与所述第一浮动栅极间隔开的暴露的侧壁; 相应的第一浮动栅极和第二浮动栅极,至少在第一和第二浮动栅极的相应暴露的侧壁上方的第二对间隔物,在第二对间隔物之间​​的结构中的源极区域,源极植入物 并且设置在第一对间隔件外侧的第一和第二控制门,并且暴露在结构的暴露的外侧部分中的结构的外侧部分和相应的漏极区域。 还提供了一种形成嵌入式闪存单元结构的方法。
    • 4. 发明授权
    • Poly etching solution to improve silicon trench for low STI profile
    • Poly蚀刻解决方案,以改善硅沟槽的低STI特性
    • US06649489B1
    • 2003-11-18
    • US10366207
    • 2003-02-13
    • Li-Wen ChangHung-Cheng SungDer-Shin ShyuHan-Ping ChenChen-Ming HuangYa-Chen Kao
    • Li-Wen ChangHung-Cheng SungDer-Shin ShyuHan-Ping ChenChen-Ming HuangYa-Chen Kao
    • H01L2176
    • H01L21/76232
    • A method of etch polysilicon adjacent to a recessed STI structure feature is described. A substrate is provided with a dielectric layer thereon and a polysilicon layer on the dielectric layer. A shallow trench is formed that extends through the polysilicon and dielectric layers into the substrate. An insulating material is used to fill the trench and is then recessed in the trench below the surface of the substrate by polishing and etching steps. A conformal buffer layer is deposited which covers the polysilicon and sidewalls of the trench above the recessed insulating layer. The buffer layer is etched back to expose the insulating layer and the polysilicon is removed by a plasma etch. A spacer comprised of a portion of the buffer layer protects the substrate during the polysilicon etch to prevent unwanted trenches from being formed adjacent to the STI structure, thereby increasing the etch process window.
    • 描述了与凹陷STI结构特征相邻的蚀刻多晶硅的方法。 衬底上设置介电层,并在电介质层上设置多晶硅层。 形成浅沟槽,其延伸穿过多晶硅和电介质层进入衬底。 绝缘材料用于填充沟槽,然后通过抛光和蚀刻步骤将其凹入到衬底表面下方的沟槽中。 沉积保形缓冲层,其覆盖凹陷绝缘层上方的沟槽的多晶硅和侧壁。 将缓冲层回蚀刻以暴露绝缘层,并且通过等离子体蚀刻去除多晶硅。 由缓冲层的一部分构成的间隔件在多晶硅蚀刻期间保护衬底以防止在STI结构附近形成不必要的沟槽,从而增加蚀刻工艺窗口。
    • 6. 发明授权
    • Methods and devices for determining writing current for memory cells
    • 用于确定存储器单元写入电流的方法和装置
    • US07102919B1
    • 2006-09-05
    • US11078171
    • 2005-03-11
    • Hung-Cheng SungDer-Shin Shyu
    • Hung-Cheng SungDer-Shin Shyu
    • G11C11/00
    • G11C11/16
    • Methods for determining writing current for memory cells. A first reference current is applied to a first operative line to switch the memory cell to a first state. A second reference current is applied to a second operative line crossing the first operative line to switch the memory cell to a second state. A first writing current is obtained according to a first ratio and the first reference current. A second writing current is obtained according to a second ratio and the second reference current. The memory cell is programmed by applying the first writing current to the first operative line and applying the second writing current to the second operative line.
    • 确定存储单元写入电流的方法。 将第一参考电流施加到第一操作线以将存储器单元切换到第一状态。 第二参考电流被施加到穿过第一操作线的第二操作线,以将存储器单元切换到第二状态。 根据第一比率和第一参考电流获得第一写入电流。 根据第二比例和第二参考电流获得第二写入电流。 通过将第一写入电流施加到第一操作线并将第二写入电流施加到第二操作线来编程存储器单元。
    • 9. 发明申请
    • METHODS AND DEVICES FOR DETERMINING WRITING CURRENT FOR MEMORY CELLS
    • 用于确定记忆细胞的写入电流的方法和装置
    • US20060203537A1
    • 2006-09-14
    • US11078171
    • 2005-03-11
    • Hung-Cheng SungDer-Shin Shyu
    • Hung-Cheng SungDer-Shin Shyu
    • G11C11/00
    • G11C11/16
    • Methods for determining writing current for memory cells. A first reference current is applied to a first operative line to switch the memory cell to a first state. A second reference current is applied to a second operative line crossing the first operative line to switch the memory cell to a second state. A first writing current is obtained according to a first ratio and the first reference current. A second writing current is obtained according to a second ratio and the second reference current. The memory cell is programmed by applying the first writing current to the first operative line and applying the second writing current to the second operative line.
    • 确定存储单元写入电流的方法。 将第一参考电流施加到第一操作线以将存储器单元切换到第一状态。 第二参考电流被施加到穿过第一操作线的第二操作线,以将存储器单元切换到第二状态。 根据第一比率和第一参考电流获得第一写入电流。 根据第二比例和第二参考电流获得第二写入电流。 通过将第一写入电流施加到第一操作线并将第二写入电流施加到第二操作线来编程存储器单元。
    • 10. 发明申请
    • High write and erase efficiency embedded flash cell
    • 高写入和擦除效率嵌入式闪存单元
    • US20050282337A1
    • 2005-12-22
    • US10870774
    • 2004-06-17
    • Der-Shin ShyuHung-Cheng SungChen-Ming Huang
    • Der-Shin ShyuHung-Cheng SungChen-Ming Huang
    • H01L21/336H01L21/4763H01L21/8247H01L27/115H01L29/423H01L29/788
    • H01L27/11521H01L27/115H01L29/42324H01L29/7885
    • An embedded flash cell structure comprising a structure, a first floating gate having an exposed side wall over the structure, a second floating gate having an exposed side wall over the structure and spaced apart from the first floating gate, a first pair of spacers over the respective first floating gate and the second floating gate, a second pair of spacers at least over the respective exposed side walls of the first and second floating gates, a source area in the structure between the second pair of spacers, a plug over the source implant, and first and second control gates outboard of the first pair of spacers and exposing outboard portions of the structure and respective drain areas in the exposed outboard portions of the structure is provided. A method of forming the embedded flash cell structure is also provided.
    • 一种嵌入式闪存单元结构,其包括结构,第一浮动栅极,其具有在所述结构上方的暴露侧壁,第二浮动栅极,具有在所述结构上并与所述第一浮动栅极间隔开的暴露的侧壁; 相应的第一浮动栅极和第二浮动栅极,至少在第一和第二浮动栅极的相应暴露的侧壁上方的第二对间隔物,在第二对间隔物之间​​的结构中的源极区域,源极植入物 并且设置在第一对间隔件外侧的第一和第二控制门,并且暴露在结构的暴露的外侧部分中的结构的外侧部分和相应的漏极区域。 还提供了一种形成嵌入式闪存单元结构的方法。