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1. 发明申请

US20100140653A1 LIGHT EMITTING DIODE STRUCTURE AND METHOD FOR FABRICATING THE SAME 审中-公开
标题翻译：发光二极管结构及其制造方法
公开(公告)号：US20100140653A1
公开(公告)日：2010-06-10
申请号：US12709105
申请日：2010-02-19
申请人： Hung-Cheng LIN , Chia-Ming LEE , Jen-Inn CHYI
发明人： Hung-Cheng LIN , Chia-Ming LEE , Jen-Inn CHYI
IPC分类号： H01L33/00
CPC分类号： H01L33/22
摘要： The present invention discloses a light emitting diode structure and a method for fabricating the same. In the present invention, a substrate is placed in a solution to form a chemical reaction layer on carved regions; the carved region is selectively etched to form a plurality of concave zones and form a plurality of convex zones; a semiconductor layer structure is epitaxially grown on the element regions and carved regions of the substrate; the semiconductor layer structure on the element regions is fabricated into a LED element with a photolithographic process.
摘要翻译：本发明公开了一种发光二极管结构及其制造方法。在本发明中，将基板放置在溶液中以在雕刻区域上形成化学反应层; 选择性地蚀刻雕刻区域以形成多个凹陷区域并形成多个凸区域; 在衬底的元件区域和雕刻区域上外延生长半导体层结构; 通过光刻工艺将元件区域上的半导体层结构制成LED元件。

2. 发明申请

US20080296601A1 Light-Emitting Diode Incorporating an Array of Light Extracting Spots 审中-公开
标题翻译：发光二极管并入一组光提取点
公开(公告)号：US20080296601A1
公开(公告)日：2008-12-04
申请号：US12180967
申请日：2008-07-28
申请人： Jen-Inn CHYI , Chia-Ming Lee , Jui-Cheng Chang , Tsung-Liang Chen , Shih-Ling Chen
发明人： Jen-Inn CHYI , Chia-Ming Lee , Jui-Cheng Chang , Tsung-Liang Chen , Shih-Ling Chen
IPC分类号： H01L33/00
CPC分类号： H01L33/02 , H01L33/12 , H01L33/20 , H01L2933/0083
摘要： A light-emitting diode includes an optical layer formed in an array of substantially equidistant light extracting spots integrated to its multi-layered structure. The array of light extracting spots includes a distribution of juxtaposed hexagon patterns. The layer thickness of the light extracting spots is less than 800 Å.
摘要翻译：发光二极管包括形成为与其多层结构集成的基本上等距的光提取点的阵列的光学层。光提取点的阵列包括并列六边形图案的分布。光提取点的层厚小于800。

3. 发明申请

US20130034919A1 METHOD FOR FABRICATING INTEGRATED ALTERNATING-CURRENT LIGHT-EMITTING-DIODE MODULE 有权
标题翻译：一体化交流发光二极管模块的制作方法
公开(公告)号：US20130034919A1
公开(公告)日：2013-02-07
申请号：US13342431
申请日：2012-01-03
申请人： Jen-Inn CHYI , Geng-Yen Lee , Wei-Sheng Lin
发明人： Jen-Inn CHYI , Geng-Yen Lee , Wei-Sheng Lin
IPC分类号： H01L33/36
CPC分类号： H01L27/15
摘要： A method for fabricating an integrated AC LED module comprises steps: forming a junction layer on a substrate, and defining a first growth area and a second growth area on the junction layer; respectively growing a Schottky diode and a LED on the first growth area and the second growth area; forming a passivation layer and a metallic layer on the Schottky diode, the LED and the substrate. Thereby, the Schottky diode is electrically connected with the LED via the metallic layer. Thus is promoted the reliability of electric connection of diodes, reduced the layout area of the module, and decreased the fabrication cost.
摘要翻译：一种用于制造集成AC LED模块的方法包括以下步骤：在衬底上形成结层，并在所述结层上限定第一生长区和第二生长区; 分别在第一个生长区和第二个生长区生长肖特基二极管和一个LED; 在肖特基二极管，LED和基板上形成钝化层和金属层。由此，肖特基二极管经由金属层与LED电连接。从而提高了二极管电连接的可靠性，减少了模块布局面积，降低了制造成本。

4. 发明申请

US20120292663A1 Structure and Method for Monolithically Fabrication Sb-Based E/D Mode MISFETs 审中-公开
标题翻译：基于Sb的E / D模式MISFET的单片结构和方法
公开(公告)号：US20120292663A1
公开(公告)日：2012-11-22
申请号：US13110938
申请日：2011-05-19
申请人： Heng-Kuang LIN , Han-Chieh HO , Pei-Chin CHIU , Jen-Inn CHYI
发明人： Heng-Kuang LIN , Han-Chieh HO , Pei-Chin CHIU , Jen-Inn CHYI
IPC分类号： H01L29/778
CPC分类号： H01L29/205 , H01L21/8252 , H01L27/0605 , H01L27/0883 , H01L27/092 , H01L27/0924 , H01L29/36 , H01L29/42376 , H01L29/785
摘要： The invention provides two Sb-based n- or p-channel layer structures as a template for MISFET and complementary MISFET development. Four types of MISFET devices and two types of complementary MISFET circuit devices can be developed based on the invented layer structures. Also, the layer structures can accommodate more than one complementary MISFETs and more than one single active MISFETs to be integrated on the same substrate monolithically.
摘要翻译：本发明提供了两个Sb基的n沟道或p沟道层结构作为MISFET和互补MISFET开发的模板。可以基于本发明的层结构开发四种类型的MISFET器件和两种类型的互补MISFET电路器件。此外，层结构可以容纳多于一个的互补MISFET和多于一个单个有源MISFET，以整体地集成在相同的衬底上。

5. 发明申请

US20130240895A1 SEMICONDUCTOR ELEMENT HAVING HIGH BREAKDOWN VOLTAGE 失效
标题翻译：具有高电压破坏的半导体元件
公开(公告)号：US20130240895A1
公开(公告)日：2013-09-19
申请号：US13571041
申请日：2012-08-09
申请人： Jen-Inn CHYI , Geng-Yen Lee , Hsueh-Hsing Liu
发明人： Jen-Inn CHYI , Geng-Yen Lee , Hsueh-Hsing Liu
IPC分类号： H01L29/205
CPC分类号： H01L29/66212 , H01L29/2003 , H01L29/4236 , H01L29/475 , H01L29/7787 , H01L29/872
摘要： A semiconductor element having a high breakdown voltage includes a substrate, a buffer layer, a semiconductor composite layer and a bias electrode. The buffer layer disposed on the substrate includes a high edge dislocation defect density area. The semiconductor composite layer disposed on the buffer layer includes a second high edge dislocation defect density area formed due to the first high edge dislocation defect density area. The bias electrode is disposed on the semiconductor composite layer. A virtual gate effect of defect energy level capturing electrons is generated due to the first and second high edge dislocation defect density areas, such that an extended depletion region expanded from the bias electrode is formed at the semiconductor composite layer. When the bias electrode receives a reverse bias, the extended depletion region reduces a leakage current and increases the breakdown voltage of the semiconductor element.
摘要翻译：具有高击穿电压的半导体元件包括衬底，缓冲层，半导体复合层和偏置电极。设置在基板上的缓冲层包括高边缘位错缺陷密度区域。设置在缓冲层上的半导体复合层包括由于第一高边缘位错缺陷密度区域而形成的第二高边缘位错缺陷密度区域。偏置电极设置在半导体复合层上。由于第一和第二高边缘位错缺陷密度区域产生缺陷能级捕获电子的虚拟栅极效应，使得在半导体复合层处形成从偏置电极扩展的扩展的耗尽区。当偏置电极接收到反向偏压时，扩展耗尽区减小漏电流并增加半导体元件的击穿电压。

6. 发明申请

US20120276722A1 METHOD FOR GROWING SEMIPOLAR NITRIDE 失效
标题翻译：生长二氧化碳的方法
公开(公告)号：US20120276722A1
公开(公告)日：2012-11-01
申请号：US13177330
申请日：2011-07-06
申请人： Jen-Inn CHYI , Hsueh-Hsing Liu , Hsien Yu Lin
发明人： Jen-Inn CHYI , Hsueh-Hsing Liu , Hsien Yu Lin
IPC分类号： H01L21/205
CPC分类号： H01L21/02639 , C30B23/025 , C30B23/04 , C30B25/04 , C30B25/186 , C30B29/403 , H01L21/02381 , H01L21/0243 , H01L21/02433 , H01L21/02458 , H01L21/0254 , H01L21/02647 , H01L33/007 , H01L33/16 , H01L33/20
摘要： A method for growing a semipolar nitride comprises steps: forming a plurality of parallel discrete trenches on a silicon substrate , each discrete trenches having a first wall and a second wall, wherein a tilt angle is formed between the surface of the silicon substrate and the first wall; forming a buffer layer on the silicon substrate and the trenches, wherein the buffer layer on the first wall has a plurality of growing zones and a plurality of non-growing zones among the growing zones and complementary to the growing zones; forming a cover layer on the buffer layer and revealing the growing zones; and growing a semipolar nitride from the growing zones of the buffer layer and covering the cover layer. Thereby cracks caused by thermal stress between the silicon substrate and semipolar nitride are decreased and the quality of the semipolar nitride film is improved.
摘要翻译：用于生长半极性氮化物的方法包括以下步骤：在硅衬底上形成多个平行的离散沟槽，每个离散的沟槽具有第一壁和第二壁，其中在硅衬底的表面和第一壁之间形成倾斜角壁; 在所述硅衬底和所述沟槽上形成缓冲层，其中所述第一壁上的所述缓冲层在所述生长区中具有多个生长区和多个非生长区，并与所述生长区互补; 在缓冲层上形成覆盖层并露出生长区; 以及从缓冲层的生长区域生长半极性氮化物并覆盖覆盖层。由此，硅衬底和半极性氮化物之间的热应力引起的裂纹减少，并且提高了半极性氮化物膜的质量。

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