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1. 发明申请

US20130034919A1 METHOD FOR FABRICATING INTEGRATED ALTERNATING-CURRENT LIGHT-EMITTING-DIODE MODULE 有权
标题翻译：一体化交流发光二极管模块的制作方法
公开(公告)号：US20130034919A1
公开(公告)日：2013-02-07
申请号：US13342431
申请日：2012-01-03
申请人： Jen-Inn CHYI , Geng-Yen Lee , Wei-Sheng Lin
发明人： Jen-Inn CHYI , Geng-Yen Lee , Wei-Sheng Lin
IPC分类号： H01L33/36
CPC分类号： H01L27/15
摘要： A method for fabricating an integrated AC LED module comprises steps: forming a junction layer on a substrate, and defining a first growth area and a second growth area on the junction layer; respectively growing a Schottky diode and a LED on the first growth area and the second growth area; forming a passivation layer and a metallic layer on the Schottky diode, the LED and the substrate. Thereby, the Schottky diode is electrically connected with the LED via the metallic layer. Thus is promoted the reliability of electric connection of diodes, reduced the layout area of the module, and decreased the fabrication cost.
摘要翻译：一种用于制造集成AC LED模块的方法包括以下步骤：在衬底上形成结层，并在所述结层上限定第一生长区和第二生长区; 分别在第一个生长区和第二个生长区生长肖特基二极管和一个LED; 在肖特基二极管，LED和基板上形成钝化层和金属层。由此，肖特基二极管经由金属层与LED电连接。从而提高了二极管电连接的可靠性，减少了模块布局面积，降低了制造成本。

2. 发明授权

US08426226B2 Method for fabricating integrated alternating-current light-emitting-diode module 有权
标题翻译：集成交流发光二极管模块的制造方法
公开(公告)号：US08426226B2
公开(公告)日：2013-04-23
申请号：US13342431
申请日：2012-01-03
申请人： Jen-Inn Chyi , Geng-Yen Lee , Wei-Sheng Lin
发明人： Jen-Inn Chyi , Geng-Yen Lee , Wei-Sheng Lin
IPC分类号： H01L21/00
CPC分类号： H01L27/15
摘要： A method for fabricating an integrated AC LED module comprises steps: forming a junction layer on a substrate, and defining a first growth area and a second growth area on the junction layer; respectively growing a Schottky diode and a LED on the first growth area and the second growth area; forming a passivation layer and a metallic layer on the Schottky diode, the LED and the substrate. Thereby, the Schottky diode is electrically connected with the LED via the metallic layer. Thus is promoted the reliability of electric connection of diodes, reduced the layout area of the module, and decreased the fabrication cost.
摘要翻译：一种用于制造集成AC LED模块的方法包括以下步骤：在衬底上形成结层，并在所述结层上限定第一生长区和第二生长区; 分别在第一个生长区和第二个生长区生长肖特基二极管和一个LED; 在肖特基二极管，LED和基板上形成钝化层和金属层。由此，肖特基二极管经由金属层与LED电连接。从而提高了二极管电连接的可靠性，减少了模块布局面积，降低了制造成本。

3. 发明申请

US20130240895A1 SEMICONDUCTOR ELEMENT HAVING HIGH BREAKDOWN VOLTAGE 失效
标题翻译：具有高电压破坏的半导体元件
公开(公告)号：US20130240895A1
公开(公告)日：2013-09-19
申请号：US13571041
申请日：2012-08-09
申请人： Jen-Inn CHYI , Geng-Yen Lee , Hsueh-Hsing Liu
发明人： Jen-Inn CHYI , Geng-Yen Lee , Hsueh-Hsing Liu
IPC分类号： H01L29/205
CPC分类号： H01L29/66212 , H01L29/2003 , H01L29/4236 , H01L29/475 , H01L29/7787 , H01L29/872
摘要： A semiconductor element having a high breakdown voltage includes a substrate, a buffer layer, a semiconductor composite layer and a bias electrode. The buffer layer disposed on the substrate includes a high edge dislocation defect density area. The semiconductor composite layer disposed on the buffer layer includes a second high edge dislocation defect density area formed due to the first high edge dislocation defect density area. The bias electrode is disposed on the semiconductor composite layer. A virtual gate effect of defect energy level capturing electrons is generated due to the first and second high edge dislocation defect density areas, such that an extended depletion region expanded from the bias electrode is formed at the semiconductor composite layer. When the bias electrode receives a reverse bias, the extended depletion region reduces a leakage current and increases the breakdown voltage of the semiconductor element.
摘要翻译：具有高击穿电压的半导体元件包括衬底，缓冲层，半导体复合层和偏置电极。设置在基板上的缓冲层包括高边缘位错缺陷密度区域。设置在缓冲层上的半导体复合层包括由于第一高边缘位错缺陷密度区域而形成的第二高边缘位错缺陷密度区域。偏置电极设置在半导体复合层上。由于第一和第二高边缘位错缺陷密度区域产生缺陷能级捕获电子的虚拟栅极效应，使得在半导体复合层处形成从偏置电极扩展的扩展的耗尽区。当偏置电极接收到反向偏压时，扩展耗尽区减小漏电流并增加半导体元件的击穿电压。

4. 发明授权

US08586995B2 Semiconductor element having high breakdown voltage 失效
标题翻译：具有高击穿电压的半导体元件
公开(公告)号：US08586995B2
公开(公告)日：2013-11-19
申请号：US13571041
申请日：2012-08-09
申请人： Jen-Inn Chyi , Geng-Yen Lee , Hsueh-Hsing Liu
发明人： Jen-Inn Chyi , Geng-Yen Lee , Hsueh-Hsing Liu
IPC分类号： H01L29/205 , H01L29/78
CPC分类号： H01L29/66212 , H01L29/2003 , H01L29/4236 , H01L29/475 , H01L29/7787 , H01L29/872
摘要： A semiconductor element having a high breakdown voltage includes a substrate, a buffer layer, a semiconductor composite layer and a bias electrode. The buffer layer disposed on the substrate includes a high edge dislocation defect density area. The semiconductor composite layer disposed on the buffer layer includes a second high edge dislocation defect density area formed due to the first high edge dislocation defect density area. The bias electrode is disposed on the semiconductor composite layer. A virtual gate effect of defect energy level capturing electrons is generated due to the first and second high edge dislocation defect density areas, such that an extended depletion region expanded from the bias electrode is formed at the semiconductor composite layer. When the bias electrode receives a reverse bias, the extended depletion region reduces a leakage current and increases the breakdown voltage of the semiconductor element.
摘要翻译：具有高击穿电压的半导体元件包括衬底，缓冲层，半导体复合层和偏置电极。设置在基板上的缓冲层包括高边缘位错缺陷密度区域。设置在缓冲层上的半导体复合层包括由于第一高边缘位错缺陷密度区域而形成的第二高边缘位错缺陷密度区域。偏置电极设置在半导体复合层上。由于第一和第二高边缘位错缺陷密度区域产生缺陷能级捕获电子的虚拟栅极效应，使得在半导体复合层处形成从偏置电极扩展的扩展的耗尽区。当偏置电极接收到反向偏压时，扩展耗尽区减小漏电流并增加半导体元件的击穿电压。

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