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1. 发明授权

US06248002B1 Obtaining the better defect performance of the fuse CMP process by adding slurry polish on more soft pad after slurry polish 有权
标题翻译：通过在浆液抛光后在更软的垫上添加浆料抛光，获得熔融CMP工艺的更好的缺陷性能
公开(公告)号：US06248002B1
公开(公告)日：2001-06-19
申请号：US09421509
申请日：1999-10-20
申请人： Hui-Ling Wang , Tong-Hua Kuan , Ying-Lang Wang , Yu-Ku Lin
发明人： Hui-Ling Wang , Tong-Hua Kuan , Ying-Lang Wang , Yu-Ku Lin
IPC分类号： B24B100
CPC分类号： B24B37/042
摘要： A method to prevent the accumulation of particle impurities on the surface of a semiconductor substrate that contains wolfram plugs during the process of polishing the surface of the wafer. The polishing sequence consists of three distinct polishing steps whereby the first two steps use hard polishing pads while the third step uses a soft polishing pad with the application of slurry during the third polish.
摘要翻译：一种在抛光晶片表面的过程中防止颗粒杂质在含有钨骨塞的半导体衬底表面积聚的方法。抛光顺序由三个不同的抛光步骤组成，其中前两个步骤使用硬抛光垫，而第三步在第三次抛光期间使用软抛光垫施加浆料。

2. 发明授权

US06287172B1 Method for improvement of tungsten chemical-mechanical polishing process 有权
标题翻译：钨化学机械抛光工艺的改进方法
公开(公告)号：US06287172B1
公开(公告)日：2001-09-11
申请号：US09465700
申请日：1999-12-17
申请人： Tong-Hua Kuan , Hui-Ling Wang , Ying-Lang Wang , Chin-Kun Lan
发明人： Tong-Hua Kuan , Hui-Ling Wang , Ying-Lang Wang , Chin-Kun Lan
IPC分类号： B24B100
CPC分类号： B24B37/345 , B24B37/0056 , B24B37/042 , B24D13/142
摘要： A multi-step chemical-mechanical polishing method for improving tungsten chemical-mechanical polishing (CMP) process is provided in the present invention. The method comprises following steps. First, a wafer is placed on a first pad of a CMP system, wherein a head fixes the wafer on the first pad. Then, the head is rotated and the wafer is polished on the first pad by using a tungsten slurry. Next, the wafer is transferred to place on a second pad of the CMP system, wherein the head fixes the wafer on the second pad. Following, the head is rotated and the wafer is polished on the second pad by using the tungsten slurry. Then, the wafer is cleaned on the second pad by using a de-ionic water. Next, the wafer is transferred to place on a third pad of the CMP system, wherein the head fixes the wafer on the third pad. Following, the wafer is cleaned on the third pad by using the de-ionic water. Last, the head is rotated and the wafer is polished on the third pad by using an oxide slurry, wherein a pH value of the tungsten slurry and a pH value of the oxide slurry are opposite.
摘要翻译：本发明提供了一种用于改善钨化学机械抛光（CMP）工艺的多步化学机械抛光方法。该方法包括以下步骤。首先，将晶片放置在CMP系统的第一焊盘上，其中头部将晶片固定在第一焊盘上。然后，头部旋转，并且通过使用钨浆料在第一焊盘上抛光晶片。接下来，将晶片转移到CMP系统的第二焊盘上，其中头部将晶片固定在第二焊盘上。接下来，头部旋转，并且通过使用钨浆料在第二垫上抛光晶片。然后，通过使用脱离子水在第二焊盘上清洁晶片。接下来，将晶片转移到CMP系统的第三焊盘上，其中头部将晶片固定在第三焊盘上。接下来，通过使用去离子水在第三垫上清洁晶片。最后，旋转头部，通过使用氧化物浆料在第三焊盘上抛光晶片，其中钨浆料的pH值和氧化物浆料的pH值相反。

3. 发明授权

US06531382B1 Use of a capping layer to reduce particle evolution during sputter pre-clean procedures 有权
标题翻译：在溅射预清洁过程中使用覆盖层来减少颗粒的发生
公开(公告)号：US06531382B1
公开(公告)日：2003-03-11
申请号：US10140662
申请日：2002-05-08
申请人： Tao Cheng , Wen-Hsin Huang , Jiun-Pyng You , Lin-June Wu , Shih-Tzung Chang , Ming-Jei Lee , Chun-Chang Chen , Yu-Ku Lin , Tong-Hua Kuan , Ying-Lang Wang
发明人： Tao Cheng , Wen-Hsin Huang , Jiun-Pyng You , Lin-June Wu , Shih-Tzung Chang , Ming-Jei Lee , Chun-Chang Chen , Yu-Ku Lin , Tong-Hua Kuan , Ying-Lang Wang
IPC分类号： H01L213205
CPC分类号： H01L21/76802 , H01L21/76838
摘要： A process for preparing a surface of a lower level metal structure, exposed at the bottom of a sub-micron diameter opening, to allow a low resistance interface to be obtained when overlaid with an upper level metal structure, has been developed. A disposable, capping insulator layer is first deposited on the composite insulator layer in which the sub-micron diameter opening will be defined in, to protect underlying components of the composite insulator from a subsequent metal pre-metal procedure. After anisotropically defining the sub-micron diameter opening in the capping insulator, and composite insulator layers, and after removal of the defining photoresist shape, an argon sputtering procedure is used to remove native oxide from the surface of the lower level metal structure. In addition to native oxide removal the argon sputtering procedure, featuring a negative DC bias applied to the substrate, also removes the capping insulator layer from the top surface of the composite insulator layer. An in situ metal deposition then allows a clean interface to result between the overlying metal layer, and the underlying plasma treated, metal surface.
摘要翻译：已经开发了制备在亚微米直径开口的底部露出的下层金属结构的表面以允许在与上层金属结构重叠时获得低电阻界面的方法。首先将一次性封盖绝缘体层沉积在复合绝缘体层上，在该复合绝缘层上将限定亚微米直径的开口，以保护复合绝缘子的下面的部件免于后续的金属预金属工艺。在各向异性地限定封盖绝缘体中的亚微米直径开口和复合绝缘体层之后，并且在去除限定的光致抗蚀剂形状之后，使用氩溅射方法从下层金属结构的表面去除自然氧化物。除了自然氧化物除去之外，具有施加到衬底的负DC偏压的氩溅射工艺也从复合绝缘体层的顶表面去除封盖绝缘体层。原位金属沉积然后允许在上覆的金属层和下面的等离子体处理的金属表面之间产生干净的界面。

4. 发明授权

US06291331B1 Re-deposition high compressive stress PECVD oxide film after IMD CMP process to solve more than 5 metal stack via process IMD crack issue 有权
标题翻译：重新沉积高压应力PECVD氧化膜经IMD CMP工艺解决超过5个金属堆叠通过工艺IMD裂纹问题
公开(公告)号：US06291331B1
公开(公告)日：2001-09-18
申请号：US09412654
申请日：1999-10-04
申请人： Ying-Lang Wang , Jowei Dun , Ming-Jer Lee , Tong-Hua Kuan
发明人： Ying-Lang Wang , Jowei Dun , Ming-Jer Lee , Tong-Hua Kuan
IPC分类号： H01L2144
CPC分类号： H01L21/76801 , H01L2224/02166 , H01L2224/05093
摘要： A new method is provided for the creation of layers of dielectric that are used for metal stack interconnect layers where the metal stack exceeds five layers. A stack of five layers of metal interconnect lines contains one layer of Intra Metal dielectric (ILD) and four layers of Inter Metal dielectric (IMD). One or more of the layers of IMD can be formed in the conventional method. One or more of the layers of IMD can be formed in the conventional method after which a layer of high compressive PECVD is deposited over this one or more layers of IMD. The layer of high compressive PECVD provides a crack resistant film that eliminates the formation of cracks in the surface of the IMD.
摘要翻译：提供了一种新的方法，用于创建用于金属堆叠互连层的电介质层，其中金属叠层超过五层。五层金属互连线的堆叠包含一层金属介电介质（ILD）和四层金属间介质（IMD）。 IMD的一个或多个层可以用常规方法形成。可以以常规方法形成IMD的一个或多个层，之后在该一个或多个IMD层上沉积高压缩PECVD层。高压缩PECVD层提供了抗裂膜，消除了在IMD表面形成裂缝。

5. 发明授权

US06645825B1 Planarization of shallow trench isolation (STI) 有权
标题翻译：浅沟槽隔离（STI）的平面化
公开(公告)号：US06645825B1
公开(公告)日：2003-11-11
申请号：US09614554
申请日：2000-07-12
申请人： Chin Kun Lan , Ting Chun Wang , Tong-Hua Kuan , Ying-Lang Wang
发明人： Chin Kun Lan , Ting Chun Wang , Tong-Hua Kuan , Ying-Lang Wang
IPC分类号： H01L2176
CPC分类号： H01L21/76229
摘要： An improved and new process for fabricating a planarized structure of shallow trench isolation (STI) embedded in a silicon substrate has been developed. The planarizing method comprises a two-step CMP process in which the first CMP step comprises chemical-mechanical polishing of silicon oxide using a first polishing slurry which is selective to silicon oxide. The time of the second CMP step is determined by selecting an overpolish thickness based on the percentage of substrate area occupied by the trench. High manufacturing yield and superior planarity for silicon oxide STI are achieved.
摘要翻译：已经开发了一种用于制造嵌入硅衬底中的浅沟槽隔离（STI）的平面化结构的改进和新工艺。平面化方法包括两步CMP工艺，其中第一CMP步骤包括使用对氧化硅选择性的第一抛光浆料进行二氧化硅的化学机械抛光。通过基于沟槽占据的衬底面积的百分比来选择过抛光厚度来确定第二CMP步骤的时间。实现了高的制造成品率和优异的氧化硅STI平坦度。

6. 发明授权

US6136680A Methods to improve copper-fluorinated silica glass interconnects 有权
标题翻译：改善铜氟化石英玻璃互连的方法
公开(公告)号：US6136680A
公开(公告)日：2000-10-24
申请号：US489498
申请日：2000-01-21
申请人： Jane-Bai Lai , Chung-Shi Liu , Tien-I Bao , Syun-Ming Jang , Chung-Long Chang , Hui-Ling Wang , Szu-An Wu , Wen-Kung Cheng , Chun-Ching Tsan , Ying-Lang Wang
发明人： Jane-Bai Lai , Chung-Shi Liu , Tien-I Bao , Syun-Ming Jang , Chung-Long Chang , Hui-Ling Wang , Szu-An Wu , Wen-Kung Cheng , Chun-Ching Tsan , Ying-Lang Wang
IPC分类号： H01L21/02 , H01L21/3105 , H01L21/321 , H01L21/768 , H01L21/44 , H01L21/4763
CPC分类号： H01L21/76825 , H01L21/02074 , H01L21/3105 , H01L21/3212 , H01L21/76826 , H01L21/76834 , H01L21/7684 , H01L21/76883
摘要： A method of forming an interconnect, comprising the following steps. A semiconductor structure is provided that has an exposed first metal contact and a dielectric layer formed thereover. An FSG layer having a predetermined thickness is then formed over the dielectric layer. A trench, having a predetermined width, is formed within the FSG layer and the dielectric layer exposing the first metal contact. A barrier layer, having a predetermined thickness, may be formed over the FSG layer and lining the trench side walls and bottom. A metal, preferably copper, is then deposited on the barrier layer to form a copper layer, having a predetermined thickness, over said barrier layer covered FSG layer, filling the lined trench and blanket filling the barrier layer covered FSG layer. The copper layer, and the barrier layer on said upper surface of said FSG layer, are planarized, exposing the upper surface of the FSG layer and forming a planarized copper filled trench. The FSG layer and planarized copper filled trench are then processed by either: (1) annealing from about 400 to 450.degree. C. for about one hour, then either NH.sub.3 or H.sub.2 plasma treating; or (2) Ar.sup.+ sputtering to ion implant Ar.sup.+ to a depth of less than about 300 .ANG. in the fluorinated silica glass layer, whereby any formed Si--OH bonds and copper oxide (metal oxide) are removed. A dielectric cap layer, having a predetermined thickness, is then formed over the processed FSG layer and the planarized copper filled trench.
摘要翻译：一种形成互连的方法，包括以下步骤。提供一种半导体结构，其具有暴露的第一金属触点和形成在其上的电介质层。然后在电介质层上形成具有预定厚度的FSG层。具有预定宽度的沟槽形成在FSG层内，并且介电层露出第一金属接触。具有预定厚度的阻挡层可以形成在FSG层之上并且衬在沟槽侧壁和底部。然后将一种金属，优选铜沉积在阻挡层上，以形成具有预定厚度的铜层，超过所述阻挡层覆盖的FSG层，填充衬里的沟槽和覆盖填充阻挡层覆盖的FSG层的毯子。所述FSG层的所述上表面上的铜层和阻挡层被平坦化，暴露出FSG层的上表面并形成平坦化的铜填充沟槽。然后通过以下步骤之一处理FSG层和平坦化的铜填充沟槽：（1）从约400至450℃的退火约1小时，然后进行NH 3或H 2等离子体处理; 或者（2）在氟化石英玻璃层中，离子注入Ar +溅射至小于约300的深度，由此除去任何形成的Si-OH键和氧化铜（金属氧化物）。然后在经处理的FSG层和平坦化的铜填充沟槽上形成具有预定厚度的电介质盖层。

7. 发明授权

US06281146B1 Plasma enhanced chemical vapor deposition (PECVD) method for forming microelectronic layer with enhanced film thickness uniformity 有权
标题翻译：用于形成具有增强的膜厚度均匀性的微电子层的等离子体增强化学气相沉积（PECVD）方法
公开(公告)号：US06281146B1
公开(公告)日：2001-08-28
申请号：US09396517
申请日：1999-09-15
申请人： Ying-Lang Wang , Hui-Ling Wang , Jowei Dun , Szu-An Wu
发明人： Ying-Lang Wang , Hui-Ling Wang , Jowei Dun , Szu-An Wu
IPC分类号： H01L2131
CPC分类号： H01L21/02164 , C23C16/402 , C23C16/5096 , H01L21/02211 , H01L21/02274 , H01L21/31612
摘要： A method for forming a microelectronic layer. There is first provided a substrate. There is then formed over the substrate the microelectronic layer while employing a plasma enhanced chemical vapor deposition (PECVD) method employing a source material gas and a carrier gas, wherein there is employed a sufficiently low plasma power, a sufficiently low source material gas:carrier gas flow rate ratio and a sufficiently high carrier gas atomic mass such that the microelectronic layer is formed with enhanced film thickness uniformity. The method may be employed for forming ion implant screen layers, such as silicon oxide ion implant screen layers, with enhanced film thickness uniformity.
摘要翻译：一种形成微电子层的方法。首先提供基板。然后在采用使用源材料气体和载气的等离子体增强化学气相沉积（PECVD）方法的基板上形成微电子层，其中采用足够低的等离子体功率，足够低的源材料气体：载体气体流量比和足够高的载气原子质量，使得微电子层形成为具有增强的膜厚均匀性。该方法可用于形成具有增强的膜厚度均匀性的离子注入屏幕层，例如氧化硅离子注入屏幕层。

8. 发明授权

US09419155B2 Sensing product and method of making 有权
标题翻译：感知产品和制作方法
公开(公告)号：US09419155B2
公开(公告)日：2016-08-16
申请号：US13343922
申请日：2012-01-05
申请人： Shih-Chieh Chang , Yu-Ku Lin , Ying-Lang Wang
发明人： Shih-Chieh Chang , Yu-Ku Lin , Ying-Lang Wang
IPC分类号： H01L31/0232 , H01L31/101 , H01L31/18
CPC分类号： H01L31/0232 , H01L31/02327 , H01L31/101 , H01L31/18
摘要： This description relates to a sensing product formed using a substrate with a plurality of epi-layers. At least a first epi-layer has a different composition than the composition of a second epi-layer. The sensing product optionally includes at least one radiation sensing element in the second epi-layer and optionally an interconnect structure over the second epi-layer. The sensing product is formed by removing the substrate and all epi-layers other than the second epi-layer. A light incident surface of the second epi-layer has a total thickness variation of less than about 0.15 μm.
摘要翻译：该描述涉及使用具有多个外延层的基板形成的感测产品。至少第一外延层具有与第二外延层的组成不同的组成。感测产品可选地包括第二外延层中的至少一个辐射感测元件以及可选地在第二外延层上的互连结构。通过去除衬底和除第二外延层之外的所有外延层形成传感产物。第二外延层的光入射表面具有小于约0.15μm的总厚度变化。

9. 发明授权

US07312149B2 Copper plating of semiconductor devices using single intermediate low power immersion step 有权
标题翻译：采用单中级低功耗浸入式半导体器件镀铜
公开(公告)号：US07312149B2
公开(公告)日：2007-12-25
申请号：US10840095
申请日：2004-05-06
申请人： Chao-Lung Chen , Kei-Wei Chen , Shih-Ho Lin , Ying-Lang Wang , Yu-Ku Lin , Ching-Hwanq Su , Po-Jen Shih , Shang-Chin Sung
发明人： Chao-Lung Chen , Kei-Wei Chen , Shih-Ho Lin , Ying-Lang Wang , Yu-Ku Lin , Ching-Hwanq Su , Po-Jen Shih , Shang-Chin Sung
IPC分类号： H01L21/44
CPC分类号： C25D7/123 , C25D3/02 , C25D5/10 , C25D5/18 , H01L21/2885
摘要： A method of electroplating a metal layer on a semiconductor device includes a sequence of biasing operations that includes a first electroplating step at a first current density followed by a second immersion step at a second current density being less than the first current density, and subsequent electroplating steps of increasing current densities beginning with a third electroplating step having a third current density that is greater than the first current density. The second, low current density immersion step improves the quality of the plating process and produces a plated film that completely fills openings such as vias and trenches and avoids hollow vias and pull-back on the bottom corners of via and trench openings. The low current density second immersion step produces an electrochemical deposition process that provides low contact resistance and therefore reduces device failure.
摘要翻译：在半导体器件上电镀金属层的方法包括一系列偏置操作，其包括第一电流密度的第一电镀步骤，随后是第二电流密度小于第一电流密度的第二浸入步骤，随后的电镀从具有大于第一电流密度的第三电流密度的第三电镀步骤开始增加电流密度的步骤。第二，低电流密度浸没步骤提高了电镀工艺的质量，并且产生完全填充诸如通孔和沟槽等开口的电镀膜，并避免了通孔和沟槽开口的底角上的中空通孔和拉回。低电流密度第二浸入步骤产生电化学沉积工艺，其提供低接触电阻并因此减少器件故障。

10. 发明授权

US06863491B2 Catch-pin water support for process chamber 失效
标题翻译：捕捉针水处理室支撑
公开(公告)号：US06863491B2
公开(公告)日：2005-03-08
申请号：US10339691
申请日：2003-01-08
申请人： Hsi-Kuei Cheng , Chun-Tse Lin , Ting-Chun Wang , Yu-Ku Lin , Ying-Lang Wang
发明人： Hsi-Kuei Cheng , Chun-Tse Lin , Ting-Chun Wang , Yu-Ku Lin , Ying-Lang Wang
IPC分类号： H01L21/687 , B23B31/16
CPC分类号： H01L21/68707 , Y10T279/1033 , Y10T279/1291 , Y10T279/19
摘要： A new and improved wafer support for supporting wafers in a process chamber such as an edge bead removal (EBR) chamber. The wafer support comprises multiple wafer support units each including a gripper block that engages an edge portion or bevel of the wafer. The gripper block is attached to an engaging and disengaging mechanism for selectively causing engagement of the gripper blocks with the wafer to support the wafer and disengagement of the gripper blocks from the wafer to release the wafer for removal of the wafer from the chamber. The gripper blocks contact little or none of the surface area on the patterned surface of the wafer to prevent or substantially reduce the formation of contact-induced defects on the wafer.
摘要翻译：一种新的和改进的晶片支撑件，用于在诸如边缘珠去除（EBR）室的处理室中支撑晶片。晶片支撑件包括多个晶片支撑单元，每个晶片支撑单元包括接合晶片的边缘部分或斜面的夹持块。夹持块附接到接合和分离机构，用于选择性地使夹持器块与晶片接合以支撑晶片，并且将夹持器块与晶片分离，以释放晶片以从晶片移除。夹持器块几乎不接触晶片的图案化表面上的表面积，以防止或基本上减少晶片上接触引起的缺陷的形成。

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