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1. 发明申请

US20050216710A1 Parallel processor with functional pipeline providing programming engines by supporting multiple contexts and critical section 有权
公开(公告)号：US20050216710A1
公开(公告)日：2005-09-29
申请号：US11092366
申请日：2005-03-29
申请人： Hugh Wilkinson , Matthew Adiletta , Gilbert Wolrich , Mark Rosenbluth , Debra Bernstein , Myles Wilde
发明人： Hugh Wilkinson , Matthew Adiletta , Gilbert Wolrich , Mark Rosenbluth , Debra Bernstein , Myles Wilde
IPC分类号： G06F15/78 , G06F9/30
CPC分类号： G06F15/8053
摘要： A system and method for employing multiple hardware contexts and programming engines in a functional pipeline partitioned to facilitate high performance data processing. The system and method includes a parallel processor that assigns system functions for processing data including programming engines that support multiple contexts arranged to provide a functional pipeline by a functional pipeline control unit that passes functional data among the programming engines.

2. 发明申请

US20050038964A1 Folding for a multi-threaded network processor 有权
标题翻译：折叠为多线程网络处理器
公开(公告)号：US20050038964A1
公开(公告)日：2005-02-17
申请号：US10642061
申请日：2003-08-14
申请人： Donald Hooper , Hugh Wilkinson , Mark Rosenbluth , Debra Bernstein , Michael Fallon , Sanjeev Jain , Myles Wilde , Gilbert Wolrich
发明人： Donald Hooper , Hugh Wilkinson , Mark Rosenbluth , Debra Bernstein , Michael Fallon , Sanjeev Jain , Myles Wilde , Gilbert Wolrich
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0842 , G06F12/0804
摘要： A mechanism to process units of data associated with a dependent data stream using different threads of execution and a common data structure in memory. Accessing the common data structure in memory for the processing uses a single read operation and a single write operation. The folding of multiple read-modify-write memory operations in such a manner for multiple multi-threaded stages of processing includes controlling a first stage, which operates on the same data unit as a second stage to pass context state information to the second stage for coherency.
摘要翻译：使用不同的执行线程和存储器中的公共数据结构来处理与依赖数据流相关联的数据单元的机制。访问存储器中用于处理的公共数据结构使用单个读取操作和单个写入操作。以多个多线程处理阶段的方式折叠多个读 - 修改 - 写存储器操作包括控制第一级，其在与第二级相同的数据单元上操作以将上下文状态信息传递到第二级，用于一致性

3. 发明申请

US20060095730A1 Expansion of compute engine code space by sharing adjacent control stores using interleaved program addresses 审中-公开
标题翻译：通过使用交错的程序地址共享相邻的控制存储来扩展计算引擎代码空间
公开(公告)号：US20060095730A1
公开(公告)日：2006-05-04
申请号：US10955643
申请日：2004-09-30
申请人： Gilbert Wolrich , Mark Rosenbluth , Matthew Adiletta , Hugh Wilkinson , Jose Niell , Rajagopal Narayanan , Sanjeev Jain
发明人： Gilbert Wolrich , Mark Rosenbluth , Matthew Adiletta , Hugh Wilkinson , Jose Niell , Rajagopal Narayanan , Sanjeev Jain
IPC分类号： G06F9/30
CPC分类号： G06F12/0607 , G06F9/3802 , G06F9/3814 , G06F9/3851
摘要： Method and apparatus to support expansion of compute engine code space by sharing adjacent control stores using interleaved addressing schemes. Instructions corresponding to an original instruction thread are partitioned into multiple interleaved sequences that are stored in respective control stores. During thread execution, instructions are retrieved from the control stores in a repeated order based on the interleaving scheme. For example, in one embodiment two compute engines share two control stores. Thus, instructions for a given thread are sequentially loaded from the control stores in an alternating manner. In another embodiment, four control stores are shared by four compute engines. In this case, the instructions in a thread are interleave using four stores, and each store is accessed every fourth instruction in the code sequence. Schemes are also provided for handling branching operations to maintain synchronized access to the control stores.
摘要翻译：通过使用交错寻址方案共享相邻控制存储器来支持计算引擎代码空间的扩展的方法和装置。与原始指令线程相对应的指令被划分为存储在相应控制存储器中的多个交错序列。在线程执行期间，基于交织方案以重复的顺序从控制存储器检索指令。例如，在一个实施例中，两个计算引擎共享两个控制存储。因此，给定线程的指令以交替方式从控制存储器顺序加载。在另一个实施例中，四个控制存储由四个计算引擎共享。在这种情况下，线程中的指令使用四个存储进行交织，并且每个存储在代码序列中每第四个指令被访问。还提供了处理分支操作以维持对控制存储的同步访问的方案。

4. 发明申请

US20050198361A1 Method and apparatus for meeting a given content throughput using at least one memory channel 审中-公开
标题翻译：用于使用至少一个存储器通道来满足给定内容吞吐量的方法和装置
公开(公告)号：US20050198361A1
公开(公告)日：2005-09-08
申请号：US10748780
申请日：2003-12-29
申请人： Prashant Chandra , Uday Naik , Alok Kumar , Ameya Varde , Donald Hooper , Debra Bernstein , Myles Wilde , Mark Rosenbluth
发明人： Prashant Chandra , Uday Naik , Alok Kumar , Ameya Varde , Donald Hooper , Debra Bernstein , Myles Wilde , Mark Rosenbluth
IPC分类号： G06F15/16 , G06F15/173
CPC分类号： H04L49/901 , H04L45/125
摘要： A method and apparatus for meeting a given content throughput using at least one memory channel is generally described. In accordance with one example embodiment of the invention, a method to meet a given content throughput using at least one memory channel comprising, comparing the size of at least a portion of received content to a capacity of a single contiguous location within at least one memory channel to meet a given throughput and determining whether to distribute the at least portion of received content across the at least one memory channel, based at least in part, on the comparison.
摘要翻译：通常描述使用至少一个存储器通道来满足给定内容吞吐量的方法和装置。根据本发明的一个示例性实施例，一种使用至少一个存储器信道来满足给定内容吞吐量的方法，包括：将接收的内容的至少一部分的大小与至少一个存储器内的单个连续位置的容量进行比较信道以满足给定的吞吐量并且至少部分地基于比较来确定是否分发穿过所述至少一个存储器信道的接收的内容的至少部分。

5. 发明申请

US20050132132A1 Software controlled content addressable memory in a general purpose execution datapath 有权
公开(公告)号：US20050132132A1
公开(公告)日：2005-06-16
申请号：US11043782
申请日：2005-01-25
申请人： Mark Rosenbluth , Gilbert Wolrich , Debra Bernstein
发明人： Mark Rosenbluth , Gilbert Wolrich , Debra Bernstein
IPC分类号： G06F9/30 , G06F9/38 , G06F12/00 , G06F12/08
CPC分类号： G06F9/30021 , G06F9/3004 , G06F9/30043 , G06F9/383 , G06F12/0842
摘要： A lookup mechanism provides an input value to a datapath element disposed in an execution datapath of a processor and causes the datapath element to compare the input value to stored identifier values. The lookup mechanism receives from the datapath element a result based on the comparison.

6. 发明申请

US20050039182A1 Phasing for a multi-threaded network processor 有权
标题翻译：分阶段的多线程网络处理器
公开(公告)号：US20050039182A1
公开(公告)日：2005-02-17
申请号：US10642053
申请日：2003-08-14
申请人： Donald Hooper , Mark Rosenbluth , Debra Bernstein , Michael Fallon , Sanjeev Jain , Gilbert Wolrich
发明人： Donald Hooper , Mark Rosenbluth , Debra Bernstein , Michael Fallon , Sanjeev Jain , Gilbert Wolrich
IPC分类号： G06F9/46
CPC分类号： G06F9/5038 , G06F2209/5018 , H04L69/12
摘要： A method of and apparatus for associating units of data with threads of a multi-threaded processor for processing, and enabling each thread to perform processing for at least two of the data units during a thread execution period. The thread execution period is divided among phases, and each of the data units processed by a thread is processed by a different one of the phases.
摘要翻译：一种用于将数据单元与多线程处理器的线程相关联以用于处理的方法和装置，并且使得每个线程能够在线程执行周期期间对至少两个数据单元执行处理。线程执行周期在各个阶段之间分割，线程处理的每个数据单元都由不同的相位进行处理。

7. 发明申请

US20060140203A1 System and method for packet queuing 审中-公开
标题翻译：分组排队的系统和方法
公开(公告)号：US20060140203A1
公开(公告)日：2006-06-29
申请号：US11026313
申请日：2004-12-28
申请人： Sanjeev Jain , Gilbert Wolrich , Mark Rosenbluth , Debra Bernstein
发明人： Sanjeev Jain , Gilbert Wolrich , Mark Rosenbluth , Debra Bernstein
IPC分类号： H04L12/28
CPC分类号： H04L49/90
摘要： Data is enqueued and dequeued using a block-based queuing structure.
摘要翻译：数据排队并使用基于块的排队结构出队。

8. 发明申请

US20060136681A1 Method and apparatus to support multiple memory banks with a memory block 审中-公开
标题翻译：支持具有存储器块的多个存储体的方法和装置
公开(公告)号：US20060136681A1
公开(公告)日：2006-06-22
申请号：US11018023
申请日：2004-12-21
申请人： Sanjeev Jain , Gilbert Wolrich , Mark Rosenbluth , Debra Bernstein
发明人： Sanjeev Jain , Gilbert Wolrich , Mark Rosenbluth , Debra Bernstein
IPC分类号： G06F13/00
CPC分类号： G06F13/1673
摘要： A memory controller system includes a memory command storage module to store commands for a plurality of memory banks. The system includes a plurality of control mechanisms, each of which includes first and second pointers, to provide, in combination with a next field in each module location, a link list of commands for a given one of the plurality of memory banks.
摘要翻译：存储器控制器系统包括用于存储多个存储器组的命令的存储器命令存储模块。该系统包括多个控制机构，每个控制机制包括第一和第二指针，以便与每个模块位置中的下一个区域组合提供多个存储体中给定的一个存储体的命令的链接列表。

9. 发明申请

US20060090039A1 Method and apparatus to enable DRAM to support low-latency access via vertical caching 失效
标题翻译：使DRAM能够通过垂直高速缓存支持低延迟访问的方法和装置
公开(公告)号：US20060090039A1
公开(公告)日：2006-04-27
申请号：US10974122
申请日：2004-10-27
申请人： Sanjeev Jain , Mark Rosenbluth , Matthew Adiletta , Gilbert Wolrich
发明人： Sanjeev Jain , Mark Rosenbluth , Matthew Adiletta , Gilbert Wolrich
IPC分类号： G06F12/00
CPC分类号： H04L12/2854 , G06F12/0862 , G06F12/0875
摘要： Method and apparatus to enable slower memory, such as dynamic random access memory (DRAM)-based memory, to support low-latency access using vertical caching. Related function metadata used for packet-processing functions, including metering and flow statistics, is stored in an external DRAM-based store. In one embodiment, the DRAM comprises double data-rate (DDR) DRAM. A network processor architecture is disclosed including a DDR assist with data cache coupled to a DRAM controller. The architecture further includes multiple compute engines used to execute various packet-processing functions. One such function is a DDR assist function that is used to pre-fetch a set of function metadata for a current packet and store the function metadata in the data cache. Subsequently, one or more packet-processing functions may operate on the function metadata by accessing it from the cache. After the functions are completed, the function metadata are written back to the DRAM-based store. The scheme provides similar performance to SRAM-based schemes, but uses much cheaper DRAM-type memory.
摘要翻译：实现较慢存储器的方法和装置，例如基于动态随机存取存储器（DRAM）的存储器，以支持使用垂直缓存的低延迟访问。用于包处理功能（包括计量和流量统计）的相关功能元数据存储在外部基于DRAM的存储中。在一个实施例中，DRAM包括双数据速率（DDR）DRAM。公开了一种网络处理器架构，其包括与DRAM控制器耦合的数据高速缓存的DDR辅助。该架构还包括用于执行各种分组处理功能的多个计算引擎。一个这样的功能是DDR辅助功能，其用于预取当前分组的一组功能元数据并将功能元数据存储在数据高速缓存中。随后，一个或多个分组处理功能可以通过从高速缓存访问功能元数据来操作。功能完成后，将功能元数据写回到基于DRAM的商店。该方案提供与基于SRAM的方案类似的性能，但使用更便宜的DRAM型存储器。

10. 发明申请

US20050018601A1 Traffic management 审中-公开
标题翻译：交通管理
公开(公告)号：US20050018601A1
公开(公告)日：2005-01-27
申请号：US10612552
申请日：2003-07-01
申请人： Suresh Kalkunte , Hugh Wilkinson , Gilbert Wolrich , Mark Rosenbluth , Donald Hooper
发明人： Suresh Kalkunte , Hugh Wilkinson , Gilbert Wolrich , Mark Rosenbluth , Donald Hooper
IPC分类号： H04L12/56 , H04Q11/04 , H04L1/00
CPC分类号： H04L12/5601 , H04L2012/561 , H04L2012/5636 , H04L2012/5679
摘要： In general, in one aspect, the disclosure describes a system to process packets received over a network. The system includes a receive process of at least one thread of a network processor to receive data of packets belonging to different flows. The system also includes a transmit process of at least one thread to transmit packets received by the receive process. A scheduler process of at least one thread populates at least one schedule of flow service based, at least in part, on quality of service characteristics associated with the different flows. The schedule identifies different flow candidates for service. The system also includes a shaper process of at least one thread to select from the candidate flows for service from the at least one schedule.
摘要翻译：一般来说，一方面，本公开描述了一种处理通过网络接收的分组的系统。该系统包括网络处理器的至少一个线程的接收处理，以接收属于不同流的分组的数据。系统还包括至少一个线程的发送过程，以发送由接收过程接收的分组。至少部分地基于与不同流相关联的服务质量特征，至少一个线程的调度器过程填充至少一个流服务调度。计划确定不同的候选候选人的服务。该系统还包括至少一个线程的整形过程，以从候选流中选择来自至少一个调度的服务。

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