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1. 发明授权

US07873933B2 Computer program for balancing power plane pin currents in a printed wiring board 有权
标题翻译：用于平衡印刷电路板中电源平面引脚电流的计算机程序
公开(公告)号：US07873933B2
公开(公告)日：2011-01-18
申请号：US11936673
申请日：2007-11-07
申请人： Hubert Harrer , Andreas Huber , Thomas-Michael Winkel
发明人： Hubert Harrer , Andreas Huber , Thomas-Michael Winkel
IPC分类号： G06F17/50 , H03K17/693
CPC分类号： H05K1/0265 , H05K2201/093 , H05K2201/09663 , H05K2201/0969 , H05K2201/10189 , Y10T29/49156
摘要： A computer program for balancing power plane pin currents in a printed wiring board (PWB) provides for reduction in pin counts required for power plane (including ground plane) connections and/or reduction in requirements for connector current handling per pin. One or more slots is introduced in the metal layer implementing the power plane that alter the current distribution in the power plane. The per-pin current profile for connector pins connected to the power plane is equalized by tuning the length of the slot(s). The slots may be dashed or made internal to the power plane metal layer to avoid weakening the metal layer for laminated multi-layer PWBs and may be shaped around a connector end when the power plane pin allocation is not uniform at the connector ends. The resulting equalization reduces either pin count required for carrying the power plane current or reduces connector pin current requirements.
摘要翻译：用于平衡印刷电路板（PWB）中的电源平面引脚电流的计算机程序提供了降低电源平面（包括接地平面）连接所需的引脚数量和/或减少每个引脚上连接器电流处理的要求。在实现改变电力平面中的电流分布的电力平面的金属层中引入一个或多个槽。连接到电源平面的连接器引脚的每引脚电流曲线通过调整插槽的长度来均衡。槽可以在电源平面金属层的内部虚线或内部形成，以避免层压的多层PWB的金属层的削弱，并且当电源平面引脚分配在连接器端不均匀时可以围绕连接器端成形。所产生的均衡减少了承载电源平面电流所需的引脚数或减少连接器引脚电流要求。

2. 发明申请

US20080059919A1 COMPUTER PROGRAM FOR BALANCING POWER PLANE PIN CURRENTS IN A PRINTED WIRING BOARD 有权
标题翻译：印刷电路板平衡电源引脚电流的计算机程序
公开(公告)号：US20080059919A1
公开(公告)日：2008-03-06
申请号：US11936673
申请日：2007-11-07
申请人： Hubert Harrer , Andreas Huber , Thomas-Michael Winkel
发明人： Hubert Harrer , Andreas Huber , Thomas-Michael Winkel
IPC分类号： G06F17/50
CPC分类号： H05K1/0265 , H05K2201/093 , H05K2201/09663 , H05K2201/0969 , H05K2201/10189 , Y10T29/49156
摘要： A computer program for balancing power plane pin currents in a printed wiring board (PWB) provides for reduction in pin counts required for power plane (including ground plane) connections and/or reduction in requirements for connector current handling per pin. One or more slots is introduced in the metal layer implementing the power plane that alter the current distribution in the power plane. The per-pin current profile for connector pins connected to the power plane is equalized by tuning the length of the slot(s). The slots may be dashed or made internal to the power plane metal layer to avoid weakening the metal layer for laminated multi-layer PWBs and may be shaped around a connector end when the power plane pin allocation is not uniform at the connector ends. The resulting equalization reduces either pin count required for carrying the power plane current or reduces connector pin current requirements.
摘要翻译：用于平衡印刷电路板（PWB）中的电源平面引脚电流的计算机程序提供了降低电源平面（包括接地平面）连接所需的引脚数量和/或减少每个引脚上连接器电流处理的要求。在实现改变电力平面中的电流分布的电力平面的金属层中引入一个或多个槽。连接到电源平面的连接器引脚的每引脚电流曲线通过调整插槽的长度来均衡。槽可以在电源平面金属层的内部虚线或内部形成，以避免层压的多层PWB的金属层的削弱，并且当电源平面引脚分配在连接器端不均匀时可以围绕连接器端成形。所产生的均衡减少了承载电源平面电流所需的引脚数或减少连接器引脚电流要求。

3. 发明授权

US06774836B2 Method for delta-noise reduction 失效
标题翻译：减少降噪的方法
公开(公告)号：US06774836B2
公开(公告)日：2004-08-10
申请号：US10462529
申请日：2003-06-16
申请人： Roland Frech , Bernd Garben , Hubert Harrer , Andreas Huber , Dierk Kaller , Erich Klink , Thomas-Michael Winkel , Wiren Dale Becker
发明人： Roland Frech , Bernd Garben , Hubert Harrer , Andreas Huber , Dierk Kaller , Erich Klink , Thomas-Michael Winkel , Wiren Dale Becker
IPC分类号： H04L1702
CPC分类号： G05F1/46
摘要： A method, digital circuit system and program product for reducing delta-I noise in a plurality of activity units connected to a common DC-supply voltage. In order to smooth the fluctuations (delta-I) of a total current demand I, and a respective resulting fluctuation of the supply voltage, a signalling scheme between said activity units and a supervisor unit which holds a system-specific “database” containing at least the current demand of each activity unit device when operating regularly. Dependent of the quantity of calculated, imminent delta-I a subset of said activity units with a respective current I demand is selected and controlled, for either temporarily delaying their beginning of activity in case of an imminent supply voltage drop, or temporarily continuing their activity with a predetermined, activity-specific NO-OP phase in case of an imminent supply voltage rise.
摘要翻译：一种用于减少连接到公共DC电源电压的多个活动单元中的Δ-I噪声的方法，数字电路系统和程序产品。为了平滑总电流需求I的波动（Δ-I）和相应的电源电压波动，所述活动单元与保持包含在系统特定的“数据库”的管理单元之间的信令方案最小化每个活动单位设备当定期运行时的当前需求。选择和控制所计算的即将来临的Delta-I的量的所述活动单元的一个子集，以便在即将发生的电源电压下降的情况下暂时延迟其开始的活动，或者暂时继续其活动在即将来临的电源电压升高的情况下具有预定的活动特定的NO-OP相。

4. 发明申请

US20080257592A1 APPARATUS FOR BALANCING POWER PLANE PIN CURRENTS IN A PRINTED WIRING BOARD USING COLLINEAR SLOTS 有权
标题翻译：用于使用COLLINEAR SLOTS在印刷线路板中平衡电力平面电流引脚电流的装置
公开(公告)号：US20080257592A1
公开(公告)日：2008-10-23
申请号：US12145502
申请日：2008-06-25
申请人： Hubert Harrer , Andreas Huber , Thomas-Michael Winkel
发明人： Hubert Harrer , Andreas Huber , Thomas-Michael Winkel
IPC分类号： H05K7/06
CPC分类号： H05K1/0265 , H05K2201/093 , H05K2201/09663 , H05K2201/0969 , H05K2201/10189 , Y10T29/49156
摘要： An apparatus for balancing power plane pin currents in a printed wiring board (PWB) provides for reduction in pin counts required for power plane (including ground plane) connections and/or reduction in requirements for connector current handling per pin. One or more slots are introduced in the metal layer implementing the power plane that alter the current distribution in the power plane. The per-pin current profile for connector pins connected to the power plane is equalized by tuning the length of the slot(s). The slots may be dashed or made internal to the power plane metal layer to avoid weakening the metal layer for laminated multi-layer PWBs and may be shaped around a connector end when the power plane pin allocation is not uniform at the connector ends. The resulting equalization reduces either pin count required for carrying the power plane current or reduces connector pin current requirements.
摘要翻译：用于平衡印刷电路板（PWB）中的电源平面引脚电流的装置提供了减少电源平面（包括接地平面）连接所需的引脚数量和/或减少每个引脚上连接器电流处理的要求。在实现改变电力平面中的电流分布的电力平面的金属层中引入一个或多个槽。连接到电源平面的连接器引脚的每引脚电流曲线通过调整插槽的长度来均衡。槽可以在电源平面金属层的内部虚线或内部形成，以避免层压的多层PWB的金属层的削弱，并且当电源平面引脚分配在连接器端不均匀时可以围绕连接器端成形。所产生的均衡减少了承载电源平面电流所需的引脚数或减少连接器引脚电流要求。

5. 发明授权

US08053675B2 Apparatus for balancing power plane pin currents in a printed wiring board using collinear slots 有权
标题翻译：用于使用共线插槽平衡印刷线路板中的电源平面引脚电流的装置
公开(公告)号：US08053675B2
公开(公告)日：2011-11-08
申请号：US12145502
申请日：2008-06-25
申请人： Hubert Harrer , Andreas Huber , Thomas-Michael Winkel
发明人： Hubert Harrer , Andreas Huber , Thomas-Michael Winkel
IPC分类号： H05K1/00 , H05K1/11 , H05K1/14
CPC分类号： H05K1/0265 , H05K2201/093 , H05K2201/09663 , H05K2201/0969 , H05K2201/10189 , Y10T29/49156
摘要： Printed wiring board (PWB) provides for reduction in pin counts required for power plane (including ground plane) connections and/or reduction in requirements for connector current handling per pin. Multiple collinear slots in the form of a dashed line are introduced in the metal layer implementing the power plane that alter the current distribution in the power plane and improve the strength of the PWB. The per-pin current profile for connector pins connected to the power plane is equalized by tuning the length of the slot(s). The slots are dashed and may be made internal to the power plane metal layer to avoid weakening the metal layer for laminated multi-layer PWBs and may be shaped around a connector end when the power plane pin allocation is not uniform at the connector ends. The resulting equalization reduces either pin count required for carrying the power plane current or reduces connector pin current requirements.
摘要翻译：印刷电路板（PWB）用于减少电源平面（包括接地层）连接所需的引脚数量和/或减少每个引脚连接器电流处理的要求。虚线形式的多个共线插槽被引入到实现电力平面的金属层中，该电力平面改变电力平面中的电流分布并提高电路板的强度。连接到电源平面的连接器引脚的每引脚电流曲线通过调整插槽的长度来均衡。槽是虚线的，并且可以在功率平面金属层的内部形成，以避免薄层层叠的多层PWB的金属层的削弱，并且当电源平面的引脚分配在连接器端不均匀时可以围绕连接器端成形。所产生的均衡减少了承载电源平面电流所需的引脚数或减少连接器引脚电流要求。

6. 发明授权

US07418779B2 Method for balancing power plane pin currents in a printed wiring board using collinear slots 有权
标题翻译：使用共线插槽平衡印刷电路板中的电源平面引脚电流的方法
公开(公告)号：US07418779B2
公开(公告)日：2008-09-02
申请号：US11050602
申请日：2005-02-03
申请人： Hubert Harrer , Andreas Huber , Thomas-Michael Winkel
发明人： Hubert Harrer , Andreas Huber , Thomas-Michael Winkel
IPC分类号： H05K3/02
CPC分类号： H05K1/0265 , H05K2201/093 , H05K2201/09663 , H05K2201/0969 , H05K2201/10189 , Y10T29/49156
摘要： A method and apparatus for balancing power plane pin currents in a printed wiring board (PWB) uses a set of collinear slots in the form of a dashed line to reduce pin counts required for power plane (including ground plane) connections and/or reduction in requirements for connector current handling per pin. The slots are introduced in the metal layer implementing the power plane that alter the current distribution in the power plane. The per-pin current profile for connector pins connected to the power plane is equalized by tuning the length of the slot(s). The slots may be shaped around a connector end when the power plane pin allocation is not uniform at the connector ends. The resulting equalization reduces either pin count required for carrying the power plane current or reduces connector pin current requirements.
摘要翻译：用于平衡印刷电路板（PWB）中的功率平面引脚电流的方法和装置使用虚线形式的一组共线时隙来减少功率平面（包括接地平面）连接所需的引脚数和/或减少针脚连接器电流处理要求。这些槽被引入实现改变电力平面中的电流分布的电力平面的金属层中。连接到电源平面的连接器引脚的每引脚电流曲线通过调整插槽的长度来均衡。当电源平面引脚分配在连接器端不均匀时，槽可以围绕连接器端成形。所产生的均衡减少了承载电源平面电流所需的引脚数或减少连接器引脚电流要求。

7. 发明申请

US20060169487A1 Method and apparatus for balancing power plane pin currents in a printed wiring board 有权
标题翻译：用于平衡印刷电路板中的电源平面引脚电流的方法和装置
公开(公告)号：US20060169487A1
公开(公告)日：2006-08-03
申请号：US11050602
申请日：2005-02-03
申请人： Hubert Harrer , Andreas Huber , Thomas-Michael Winkel
发明人： Hubert Harrer , Andreas Huber , Thomas-Michael Winkel
IPC分类号： H05K7/06
CPC分类号： H05K1/0265 , H05K2201/093 , H05K2201/09663 , H05K2201/0969 , H05K2201/10189 , Y10T29/49156
摘要： A method and apparatus for balancing power plane pin currents in a printed wiring board (PWB) provides for reduction in pin counts required for power plane (including ground plane) connections and/or reduction in requirements for connector current handling per pin. One or more slots is introduced in the metal layer implementing the power plane that alter the current distribution in the power plane. The per-pin current profile for connector pins connected to the power plane is equalized by tuning the length of the slot(s). The slots may be dashed or made internal to the power plane metal layer to avoid weakening the metal layer for laminated multi-layer PWBs and may be shaped around a connector end when the power plane pin allocation is not uniform at the connector ends. The resulting equalization reduces either pin count required for carrying the power plane current or reduces connector pin current requirements.
摘要翻译：用于平衡印刷电路板（PWB）中的电源平面引脚电流的方法和装置提供了降低电源平面（包括接地平面）连接所需的引脚数量和/或减少每引脚对连接器电流处理的要求。在实现改变电力平面中的电流分布的电力平面的金属层中引入一个或多个槽。连接到电源平面的连接器引脚的每引脚电流曲线通过调整插槽的长度来均衡。槽可以在电源平面金属层的内部虚线或内部形成，以避免层压的多层PWB的金属层的削弱，并且当电源平面引脚分配在连接器端不均匀时可以围绕连接器端成形。所产生的均衡减少了承载电源平面电流所需的引脚数或减少连接器引脚电流要求。

8. 发明授权

US08805132B2 Integrated circuit package connected to a data transmission medium 有权
标题翻译：集成电路封装连接到数据传输介质
公开(公告)号：US08805132B2
公开(公告)日：2014-08-12
申请号：US13312327
申请日：2011-12-06
申请人： Harry Barowski , Thomas Brunschwiler , Roger F. Dangel , Hubert Harrer , Andreas Huber , Norbert M. Meier , Bruno Michel , Tim Niggemeier , Stephan Paredes , Jochen Supper , Jonas R. Weiss
发明人： Harry Barowski , Thomas Brunschwiler , Roger F. Dangel , Hubert Harrer , Andreas Huber , Norbert M. Meier , Bruno Michel , Tim Niggemeier , Stephan Paredes , Jochen Supper , Jonas R. Weiss
IPC分类号： G02B6/12 , G02B6/26 , H01L23/02 , H01L23/48 , H01L23/52 , H01L21/00 , G02B6/43 , H01L25/065 , H01L23/522
CPC分类号： G02B6/43 , H01L23/3128 , H01L23/481 , H01L23/5226 , H01L24/03 , H01L24/05 , H01L24/13 , H01L24/14 , H01L24/16 , H01L25/0657 , H01L2224/03464 , H01L2224/0401 , H01L2224/05009 , H01L2224/051 , H01L2224/05147 , H01L2224/05184 , H01L2224/05655 , H01L2224/131 , H01L2224/14183 , H01L2224/16145 , H01L2224/16195 , H01L2224/16225 , H01L2225/06513 , H01L2225/06517 , H01L2225/06534 , H01L2225/06551 , H01L2225/06565 , H01L2924/14 , H01L2924/1533 , H01L2924/014
摘要： An integrated circuit coupling device includes an integrated circuit package with N integrated circuit layers (L1-LN) arranged as a 3D stack; and a data transmission medium with n data transmission layers (l1-ln), wherein n≧1 and N≧2, and wherein the N integrated circuit layers are electrically connectable to the n data transmission layers.
摘要翻译：集成电路耦合装置包括具有以3D叠层排列的N个集成电路层（L1-LN）的集成电路封装; 以及具有n个数据传输层（111-1）的数据传输介质，其中n≥1且N≥2，并且其中所述N个集成电路层可电连接到所述n个数据传输层。

9. 发明申请

US20120189243A1 TRANSFERRING HEAT THROUGH AN OPTICAL LAYER OF INTEGRATED CIRCUITRY 有权
标题翻译：通过整合电路的光学层传输热量
公开(公告)号：US20120189243A1
公开(公告)日：2012-07-26
申请号：US13010184
申请日：2011-01-20
申请人： Harry Barowski , Thomas Brunschwiler , Roger F. Dangel , Hubert Harrer , Andreas Huber , Norbert M. Meier , Bruno Michel , Tim Niggemeier , Stephan Paredes , Jochen Supper , Jonas R. Weiss
发明人： Harry Barowski , Thomas Brunschwiler , Roger F. Dangel , Hubert Harrer , Andreas Huber , Norbert M. Meier , Bruno Michel , Tim Niggemeier , Stephan Paredes , Jochen Supper , Jonas R. Weiss
IPC分类号： G02B6/12 , G06F17/50
CPC分类号： H01L23/367 , G02B6/12 , G02B6/122 , G02B6/4269 , G02B6/4272 , G02B6/43 , G02B2006/12147 , G06F17/5022 , G06F17/5068 , G06F17/5077 , H01L2224/16225 , H01L2924/15311
摘要： An integrated circuitry structure includes at least first and second regions. An optical layer includes optical waveguides. A heat-conductive material transfers heat from at least the second region through the optical layer to a heat sink.
摘要翻译：集成电路结构至少包括第一和第二区域。光学层包括光波导。导热材料将热量从至少第二区域传递通过光学层到散热器。

10. 发明申请

US20120105144A1 Optimized Semiconductor Packaging in a Three-Dimensional Stack 有权
公开(公告)号：US20120105144A1
公开(公告)日：2012-05-03
申请号：US12914644
申请日：2010-10-28
申请人： Harry Barowski , Thomas Brunschwiler , Hubert Harrer , Andreas Huber , Bruno Michel , Tim Niggemeier , Stephan Paredes , Jochen Supper
发明人： Harry Barowski , Thomas Brunschwiler , Hubert Harrer , Andreas Huber , Bruno Michel , Tim Niggemeier , Stephan Paredes , Jochen Supper
IPC分类号： H01L25/00 , H01L21/50
CPC分类号： H01L25/0657 , H01L25/105 , H01L25/16 , H01L2225/06513 , H01L2225/06589 , H01L2225/1052 , H01L2225/1088 , H01L2924/0002 , H01L2924/09701 , Y10T29/41 , H01L2924/00
摘要： A mechanism is provided for optimizing semiconductor packing in a three-dimensional (3D) very-large-scale integration (VLSI) device. The 3D VLSI device comprises a processor layer coupled, via a first set of coupling devices, to at least one signaling and input/output (I/O) layer. The 3D VLSI device further comprises a power delivery layer coupled, via a second set of coupling devices, to the processor layer. In the 3D VLSI device the power delivery layer is dedicated to only delivering power and does not provide data communication signals to the elements of the three-dimensional VLSI device, and the at least one signaling and input/output (I/O) layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer.

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