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1. 发明授权

US6063661A Method for forming a bottom polysilicon electrode of a stacked capacitor for DRAM 失效
标题翻译：用于形成用于DRAM的堆叠电容器的底部多晶硅电极的方法
公开(公告)号：US6063661A
公开(公告)日：2000-05-16
申请号：US603643
申请日：1996-02-20
申请人： Huang-Chung Cheng , Huan-Ping Su , Han-Wen Liu
发明人： Huang-Chung Cheng , Huan-Ping Su , Han-Wen Liu
IPC分类号： H01L21/02 , H01L21/8242
CPC分类号： H01L28/84 , H01L28/75
摘要： A method for forming a bottom polysilicon electrode of a stacked capacitor for DRAMs makes use of a double-layered polysilicon structure and a phosphoric acid etching. When the double-layered polysilicon structure is etched with the phosphoric acid, the polysilicon grain boundary is etched at a rate faster than the polysilicon grain itself so as to enable the formation of a rugged surface and thus increases the total surface area.
摘要翻译：用于形成用于DRAM的层叠电容器的底部多晶硅电极的方法利用双层多晶硅结构和磷酸蚀刻。当用磷酸蚀刻双层多晶硅结构时，以比多晶硅颗粒本身更快的速率蚀刻多晶硅晶界，从而能够形成粗糙表面，从而增加总表面积。

2. 发明授权

US5504021A Method of fabricating thin O/N/O stacked dielectric for high-density DRAMs 失效
标题翻译：制造用于高密度DRAM的薄O / N / O堆叠电介质的方法
公开(公告)号：US5504021A
公开(公告)日：1996-04-02
申请号：US290359
申请日：1994-08-15
申请人： Gary Hong , Huang-Chung Cheng , Huan-Ping Su , Han-Wen Liu
发明人： Gary Hong , Huang-Chung Cheng , Huan-Ping Su , Han-Wen Liu
IPC分类号： H01L21/02 , H01L21/70
CPC分类号： H01L28/40 , Y10S438/954
摘要： A method of fabricating a super thin O/N/O stacked dielectric by oxidizing a thin nitride layer in low pressure oxygen for high-density DRAMs is disclosed. A thin nitride layer with a thickness of approximately 20 .ANG. to 60 .ANG. is formed over the surface of a silicon substrate. The nitride layer is oxidized in pure oxygen ambient of 0.01 Torr to 76 Torr at a temperature from 750.degree. C. to 950.degree. C. for approximately 10 to 60 minutes. A super thin oxide/nitride/oxide (O/N/O) stacked dielectric exhibiting a low leakage current and high reliability for use in high-density DRAMs is formed by the aforementioned low-pressure dry-oxidation procedure.
摘要翻译：公开了一种通过在低压氧气中氧化薄层氮化物层来制造超薄O / N / O堆叠电介质的方法，用于高密度DRAM。在硅衬底的表面上形成厚度约为20至60的薄氮化物层。氮化物层在纯氧气氛中在0.01Torr至76Torr的温度下在750℃至950℃下氧化约10至60分钟。通过上述低压干法氧化法形成超低氧化物/氮化物/氧化物（O / N / O）堆叠电介质，其表现出低泄漏电流和高可靠性，用于高密度DRAM。

3. 发明授权

US5970360A DRAM cell with a roughened poly-Si electrode 失效
标题翻译：具有粗糙多晶硅电极的DRAM单元
公开(公告)号：US5970360A
公开(公告)日：1999-10-19
申请号：US764872
申请日：1996-12-03
申请人： Huang-Chung Cheng , Han-Wen Liu , Stewart Huang , Roger Yen
发明人： Huang-Chung Cheng , Han-Wen Liu , Stewart Huang , Roger Yen
IPC分类号： H01L21/02 , H01L21/3213 , H01L21/8242
CPC分类号： H01L27/10852 , H01L21/32134 , H01L28/84 , Y10S438/96 , Y10S438/964
摘要： A porous silicon layer is created by using wet etching to etch a polysilicon layer. In preferred embodiment, the polysilicon layer is treated by H.sub.3 PO.sub.4 solution at 60-165.degree. C. for about 3-200 minutes. The porous silicon layer is subsequently treated by using a SC-1 solution at a temperature about 50-100.degree. C. for about 5-30 minutes to form a roughened polysilicon layer. The SC-1 solution is composed of NH.sub.4 OH, H.sub.2 O.sub.2 and H.sub.2 O. The volume ratio for the three compounds of said SC-1 is NH.sub.4 OH:H.sub.2 O.sub.2 :H.sub.2 O=0.1-5:0.1-5:1-20. The next step of the formation is the deposition of a dielectric film along the roughened surface of the micro-islands polysilicon layers. A conductive layer is deposited over the dielectric film. Next, photolithgraphy and etching process are used to etch the conductive layer, the dielectric film and the micro-islands polysilicon layer into a portion of the layer.
摘要翻译：通过使用湿蚀刻来蚀刻多晶硅层来产生多孔硅层。在优选的实施方案中，多晶硅层在60-165℃下用H 3 PO 4溶液处理约3-200分钟。随后通过在约50-100℃的温度下使用SC-1溶液处理多孔硅层约5-30分钟以形成粗糙多晶硅层。 SC-1溶液由NH4OH，H2O2和H2O组成。所述SC-1的三种化合物的体积比为NH 4 OH:H 2 O 2 :H 2 O = 0.1-5：0.1-5：1-20。形成的下一步是沿着微岛多晶硅层的粗糙化表面沉积电介质膜。导电层沉积在电介质膜上。接下来，使用光刻和蚀刻工艺将导电层，电介质膜和微岛多晶硅层刻蚀成该层的一部分。

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