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1. 发明授权

US6063661A Method for forming a bottom polysilicon electrode of a stacked capacitor for DRAM 失效
标题翻译：用于形成用于DRAM的堆叠电容器的底部多晶硅电极的方法
公开(公告)号：US6063661A
公开(公告)日：2000-05-16
申请号：US603643
申请日：1996-02-20
申请人： Huang-Chung Cheng , Huan-Ping Su , Han-Wen Liu
发明人： Huang-Chung Cheng , Huan-Ping Su , Han-Wen Liu
IPC分类号： H01L21/02 , H01L21/8242
CPC分类号： H01L28/84 , H01L28/75
摘要： A method for forming a bottom polysilicon electrode of a stacked capacitor for DRAMs makes use of a double-layered polysilicon structure and a phosphoric acid etching. When the double-layered polysilicon structure is etched with the phosphoric acid, the polysilicon grain boundary is etched at a rate faster than the polysilicon grain itself so as to enable the formation of a rugged surface and thus increases the total surface area.
摘要翻译：用于形成用于DRAM的层叠电容器的底部多晶硅电极的方法利用双层多晶硅结构和磷酸蚀刻。当用磷酸蚀刻双层多晶硅结构时，以比多晶硅颗粒本身更快的速率蚀刻多晶硅晶界，从而能够形成粗糙表面，从而增加总表面积。

2. 发明授权

US5504021A Method of fabricating thin O/N/O stacked dielectric for high-density DRAMs 失效
标题翻译：制造用于高密度DRAM的薄O / N / O堆叠电介质的方法
公开(公告)号：US5504021A
公开(公告)日：1996-04-02
申请号：US290359
申请日：1994-08-15
申请人： Gary Hong , Huang-Chung Cheng , Huan-Ping Su , Han-Wen Liu
发明人： Gary Hong , Huang-Chung Cheng , Huan-Ping Su , Han-Wen Liu
IPC分类号： H01L21/02 , H01L21/70
CPC分类号： H01L28/40 , Y10S438/954
摘要： A method of fabricating a super thin O/N/O stacked dielectric by oxidizing a thin nitride layer in low pressure oxygen for high-density DRAMs is disclosed. A thin nitride layer with a thickness of approximately 20 .ANG. to 60 .ANG. is formed over the surface of a silicon substrate. The nitride layer is oxidized in pure oxygen ambient of 0.01 Torr to 76 Torr at a temperature from 750.degree. C. to 950.degree. C. for approximately 10 to 60 minutes. A super thin oxide/nitride/oxide (O/N/O) stacked dielectric exhibiting a low leakage current and high reliability for use in high-density DRAMs is formed by the aforementioned low-pressure dry-oxidation procedure.
摘要翻译：公开了一种通过在低压氧气中氧化薄层氮化物层来制造超薄O / N / O堆叠电介质的方法，用于高密度DRAM。在硅衬底的表面上形成厚度约为20至60的薄氮化物层。氮化物层在纯氧气氛中在0.01Torr至76Torr的温度下在750℃至950℃下氧化约10至60分钟。通过上述低压干法氧化法形成超低氧化物/氮化物/氧化物（O / N / O）堆叠电介质，其表现出低泄漏电流和高可靠性，用于高密度DRAM。

3. 发明授权

US06897566B2 Encapsulated semiconductor package free of chip carrier 失效
标题翻译：封装半导体封装无芯片载体
公开(公告)号：US06897566B2
公开(公告)日：2005-05-24
申请号：US10179793
申请日：2002-06-24
申请人： Huan-Ping Su
发明人： Huan-Ping Su
IPC分类号： H01L21/56 , H01L23/31 , H01L23/28 , H01L23/48
CPC分类号： H01L23/3114 , H01L21/56 , H01L2224/05571 , H01L2224/05573 , H01L2224/131 , H01L2224/16 , H01L2224/73104 , H01L2924/00013 , H01L2924/014 , H01L2224/13099
摘要： A semiconductor package and a method for fabricating the same are proposed. A chip has an active surface, and an opposing non-active surface. A plurality of conductive elements are mounted on the active surface and electrically connected to the chip. A first encapsulant is formed on the active surface of the chip, for encapsulating the active surface and conductive elements, wherein end portions of the conductive elements are exposed to outside of the first encapsulant, and adapted to be recessed in position with respect to an exposed surface of the first encapsulant. A plurality of conductive media are implanted at end portions of the conductive elements, allowing the chip to be electrically connected to an external device by the conductive elements and conductive media. A second encapsulant is formed on the non-active surface of the chip, and cooperates with the first encapsulant to provide mechanical strength for the semiconductor package.
摘要翻译：提出了一种半导体封装及其制造方法。芯片具有活性表面和相对的非活性表面。多个导电元件安装在有源表面上并与芯片电连接。第一密封剂形成在芯片的有源表面上，用于封装有源表面和导电元件，其中导电元件的端部暴露于第一密封剂的外部，并且适于相对于暴露的第一密封剂的表面。多个导电介质被注入在导电元件的端部，允许芯片通过导电元件和导电介质与外部器件电连接。第二密封剂形成在芯片的非活性表面上，并与第一密封剂配合以提供半导体封装的机械强度。

4. 发明授权

US06709894B2 Semiconductor package and method for fabricating the same 有权
标题翻译：半导体封装及其制造方法
公开(公告)号：US06709894B2
公开(公告)日：2004-03-23
申请号：US10170665
申请日：2002-06-12
申请人： Chung-Che Tsai , Wei-Heng Shan , Huan-Ping Su
发明人： Chung-Che Tsai , Wei-Heng Shan , Huan-Ping Su
IPC分类号： H01L2144
CPC分类号： H01L25/0652 , H01L24/45 , H01L24/73 , H01L24/97 , H01L2224/32145 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/83194 , H01L2224/97 , H01L2924/01023 , H01L2924/01033 , H01L2924/01047 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/3025 , H01L2924/00014 , H01L2224/83 , H01L2224/85 , H01L2224/92247 , H01L2924/00012 , H01L2924/00
摘要： A semiconductor package and a fabrication method thereof are provided. A plurality of first chips are mounted on and electrically connected to a substrate plate. A shielding structure including a shielding portion and a supporting portion is mounted on the substrate plate, wherein the supporting portion abuts against the substrate plate, and the shielding portion is formed with a plurality of openings corresponding in position to the first chips. An adhesive is applied through the openings to form adhesive layers respectively on the first chips. After removing the shielding structure from the substrate plate, a plurality of second chips are respectively stacked on the adhesive layers and electrically connected to the substrate plate. By performing molding and singulating processes, the packaged structure is singulated to form individual semiconductor packages. It is a characteristic advantage of forming the adhesive layers in a batch manner, making fabrication costs and time significantly reduced.
摘要翻译：提供半导体封装及其制造方法。多个第一芯片安装在基板上并电连接到基板。包括屏蔽部分和支撑部分的屏蔽结构安装在基板上，其中支撑部分抵靠基板，并且屏蔽部分形成有与第一芯片相对应的多个开口。通过开口施加粘合剂以在第一芯片上分别形成粘合剂层。在从基板移除屏蔽结构之后，将多个第二芯片分别堆叠在粘合剂层上并电连接到基板。通过进行成形和分割工艺，将封装结构单个化以形成单独的半导体封装。以间歇形式形成粘合剂层的特征在于使制造成本和时间显着降低。

5. 外观设计

USD570800S1 ISM-band printed antenna for a portion of a circuit board 有权
标题翻译：用于电路板一部分的ISM带式印刷天线
公开(公告)号：USD570800S1
公开(公告)日：2008-06-10
申请号：US29250640
申请日：2006-11-27
申请人： Hui-Mei Chen , Wei-Hsiu Hsu , Huan-Ping Su , Chien-Hsin Su
设计人： Hui-Mei Chen , Wei-Hsiu Hsu , Huan-Ping Su , Chien-Hsin Su

6. 发明授权

US06859056B2 Test fixture for semiconductor package and test method of using the same 失效
标题翻译：用于半导体封装的测试夹具及其使用的测试方法
公开(公告)号：US06859056B2
公开(公告)日：2005-02-22
申请号：US10176147
申请日：2002-06-20
申请人： Jin-Chuan Bai , Huan-Ping Su , Soon-Aik Lu
发明人： Jin-Chuan Bai , Huan-Ping Su , Soon-Aik Lu
IPC分类号： G01R1/04 , G01R31/02
CPC分类号： G01R1/0408
摘要： A test fixture for semiconductor packages and a test method of using the test fixture are proposed. The test fixture is composed of a circuit board, an interposer and a covering member. The circuit board is used to accommodate semiconductor packages and electrically connect the semiconductor packages to a test device. The interposer is mounted on the circuit board, and formed with through holes for receiving the semiconductor packages therein. The covering member is attached onto the interposer, and provided with elastic mechanisms for holding the semiconductor packages in position. By using the test fixture, semiconductor packages can be firmly coupled to the test device where functional tests are performed.
摘要翻译：提出了半导体封装的测试夹具和使用测试夹具的测试方法。测试夹具由电路板，插入件和覆盖件构成。电路板用于容纳半导体封装并将半导体封装电连接到测试装置。插入器安装在电路板上，并形成有用于在其中接收半导体封装的通孔。覆盖构件附接到插入件上，并且设置有用于将半导体封装保持在适当位置的弹性机构。通过使用测试夹具，半导体封装可以牢固地耦合到执行功能测试的测试设备。

7. 发明申请

US20100272261A1 Data Security Transmission Wirelessly with Zigbee Chips 审中-公开
标题翻译：数据安全传输无线与Zigbee芯片
公开(公告)号：US20100272261A1
公开(公告)日：2010-10-28
申请号：US12430276
申请日：2009-04-27
申请人： Chih-Yuan Su , Chun-Chin Chen , Chun-Yi Chai , Huan-Ping Su
发明人： Chih-Yuan Su , Chun-Chin Chen , Chun-Yi Chai , Huan-Ping Su
IPC分类号： H04L9/00
CPC分类号： H04L9/0877 , H04L9/083 , H04L63/062 , H04L63/18 , H04L2209/805 , H04W12/04031 , H04W84/18
摘要： A wireless network system for data transmitting securely is disclosed. The system comprises a central control end for generating a cipher password per predetermined time unit. The central control end has a first Zigbee chip, a computer terminal for a user to input parameters, and a cryptographic algorithm program provided wherein the cryptographic algorithm program and the parameters are provided for password encryption using the cryptographic algorithm program is run by a microprocessor of the first Zigbee chip. The system also comprises a data transmitting end and a several data receiving ends. The data transmitting end using the Zigbee decrypts the cipher password and encrypts the data file using the plain password and the Zigbee chip. The data receiving ends using the Zigbee decrypt the cipher password and decrypt the cipher data file into plain data file by the WiFi chips using plain password.
摘要翻译：公开了一种用于数据传输安全的无线网络系统。该系统包括用于每预定时间单位产生密码密码的中央控制端。中央控制端具有第一Zigbee芯片，用于用户输入参数的计算机终端，以及提供的加密算法程序，其中使用密码算法程序为密码加密提供密码算法程序和参数，由微处理器第一个Zigbee芯片。该系统还包括数据发送端和几个数据接收端。使用Zigbee的数据发送端解密密码，并使用纯密码和Zigbee芯片加密数据文件。使用Zigbee数据接收结束解密密码密码，并通过WiFi芯片使用纯密码将密码数据文件解密为普通数据文件。

8. 发明授权

US06956741B2 Semiconductor package with heat sink 失效
标题翻译：半导体封装带散热片
公开(公告)号：US06956741B2
公开(公告)日：2005-10-18
申请号：US10659528
申请日：2003-09-09
申请人： Huan-Ping Su
发明人： Huan-Ping Su
IPC分类号： H01L23/31 , H01L23/367 , H01L25/065 , H05K7/20
CPC分类号： H01L24/32 , H01L23/3128 , H01L23/3677 , H01L24/48 , H01L25/0657 , H01L2224/05599 , H01L2224/32057 , H01L2224/32188 , H01L2224/32225 , H01L2224/45099 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/83385 , H01L2224/85399 , H01L2225/0651 , H01L2225/06565 , H01L2225/06589 , H01L2924/00014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01087 , H01L2924/15151 , H01L2924/15311 , H01L2924/181 , H01L2924/3025 , H01L2924/351 , H01L2924/00 , H01L2924/3512 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： A semiconductor package with a heat sink is provided, having a substrate formed with at least one opening penetrating therethrough. A heat sink is mounted on a surface of the substrate same as for forming solder balls and seals one end of the opening by a thermally conductive adhesive. At least one chip is mounted on the other surface of the substrate opposite to the heat sink via the thermally conductive adhesive and covers the other end of the opening. The thermally conductive adhesive is filled in the opening between the substrate and the heat sink and allows heat produced by the chip to be dissipated through a shorter thermally conductive path. By the above arrangement with the heat sink being mounted between the chip and an external device, the heat sink provides electromagnetic shielding between the chip and the external device and enhances electrical performance of the semiconductor package.
摘要翻译：提供了具有散热器的半导体封装，其具有形成有至少一个穿透其中的开口的基板。散热器安装在基板的表面上，与形成焊球相同，并用导热粘合剂密封开口的一端。至少一个芯片通过导热粘合剂安装在与散热器相对的基板的另一个表面上，并覆盖开口的另一端。导热粘合剂填充在基板和散热器之间的开口中，并且允许由芯片产生的热量通过较短的导热路径消散。通过将散热器安装在芯片和外部设备之间的上述布置，散热器在芯片和外部设备之间提供电磁屏蔽并增强半导体封装的电气性能。

9. 发明授权

US06933178B1 Method of manufacturing semiconductor packages and a clamping device for manufacturing a semiconductor package 失效
标题翻译：制造半导体封装的方法和用于制造半导体封装的夹紧装置
公开(公告)号：US06933178B1
公开(公告)日：2005-08-23
申请号：US10829411
申请日：2004-04-20
申请人： Huan-Ping Su
发明人： Huan-Ping Su
IPC分类号： H01L21/44 , H01L21/56 , H01L23/31
CPC分类号： H01L24/97 , H01L21/565 , H01L23/3128 , H01L24/45 , H01L24/48 , H01L24/83 , H01L2224/2919 , H01L2224/32225 , H01L2224/45144 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/83192 , H01L2224/838 , H01L2224/92 , H01L2224/97 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01033 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/014 , H01L2924/0665 , H01L2924/09701 , H01L2924/15311 , H01L2924/181 , H01L2924/351 , H01L2224/85 , H01L2224/83 , H01L2224/92247 , H01L2924/00 , H01L2924/3512 , H01L2224/05599 , H01L2924/00012
摘要： A method of manufacturing semiconductor packages is proposed. A die carrier is provided having a plurality of substrate units. At least one semiconductor die is mounted on each substrate unit by an adhesive. Then the die carrier mounted with the dies is cured in a jig fixture. The jig fixture has a submold and at least one exhaust passage communicated with an external exhauster. Air in the jig fixture is drawn out by the external exhauster through the exhaust passage to form a negative-pressure environment in the jig fixture. The negative-pressure environment generates an attraction force to secure the dies to the submold and counteract thermal stresses produced in the die carrier, thereby preventing die cracking, warpage and delamination from occurrence, such that the planarity of the die carrier is assured and solder balls can be precisely secured to the die carrier in position.
摘要翻译：提出了制造半导体封装的方法。提供具有多个基板单元的模具载体。至少一个半导体管芯通过粘合剂安装在每个衬底单元上。然后，安装有模具的模具载体在夹具夹具中固化。夹具夹具具有子模具和至少一个与外部排气装置连通的排气通道。夹具夹具中的空气通过排气通道由外部排气器抽出，从而在夹具夹具中形成负压环境。负压环境产生吸引力以将模具固定到子模具并抵消在模具载体中产生的热应力，从而防止模具开裂，翘曲和脱层发生，从而确保模具载体的平面性，并且焊球可以精确地固定到模具托架就位。

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