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1. 发明申请

US20080224136A1 IMAGE SENSOR AND FABRICATION METHOD THEREOF 有权
标题翻译：图像传感器及其制造方法
公开(公告)号：US20080224136A1
公开(公告)日：2008-09-18
申请号：US11686957
申请日：2007-03-15
申请人： Hsin-Heng Wang , Chiu-Tsung Huang , Shih-Siang Lin
发明人： Hsin-Heng Wang , Chiu-Tsung Huang , Shih-Siang Lin
IPC分类号： H01L31/0232 , H01L31/18
CPC分类号： H01L27/14632 , H01L27/1463 , H01L27/14665 , H01L27/14687 , H01L27/14689
摘要： An image sensor contains a semiconductor substrate, a plurality of pixels defined on the semiconductor substrate, a photo conductive layer and a transparent conductive layer formed on the pixel electrodes of the pixels in order, and a shield device positioned between any two adjacent pixel electrodes. The shield device has a shield electrode and an isolation structure surrounding the shield electrode so that the shield electrode is isolated from the pixel electrodes and the photo conductive layer by the isolation structure.
摘要翻译：图像传感器包含半导体衬底，在半导体衬底上限定的多个像素，依次形成在像素的像素电极上的光导电层和透明导电层，以及位于任意两个相邻像素电极之间的屏蔽器件。屏蔽装置具有屏蔽电极和围绕屏蔽电极的隔离结构，使得屏蔽电极通过隔离结构与像素电极和光电导层隔离。

2. 发明授权

US07671385B2 Image sensor and fabrication method thereof 有权
标题翻译：图像传感器及其制造方法
公开(公告)号：US07671385B2
公开(公告)日：2010-03-02
申请号：US11686957
申请日：2007-03-15
申请人： Hsin-Heng Wang , Chiu-Tsung Huang , Shih-Siang Lin
发明人： Hsin-Heng Wang , Chiu-Tsung Huang , Shih-Siang Lin
IPC分类号： H01L31/0224 , H01L31/075
CPC分类号： H01L27/14632 , H01L27/1463 , H01L27/14665 , H01L27/14687 , H01L27/14689
摘要： An image sensor contains a semiconductor substrate, a plurality of pixels defined on the semiconductor substrate, a photo conductive layer and a transparent conductive layer formed on the pixel electrodes of the pixels in order, and a shield device positioned between any two adjacent pixel electrodes. The shield device has a shield electrode and an isolation structure surrounding the shield electrode so that the shield electrode is isolated from the pixel electrodes and the photo conductive layer by the isolation structure.
摘要翻译：图像传感器包含半导体衬底，在半导体衬底上限定的多个像素，依次形成在像素的像素电极上的光导电层和透明导电层，以及位于任意两个相邻像素电极之间的屏蔽器件。屏蔽装置具有屏蔽电极和围绕屏蔽电极的隔离结构，使得屏蔽电极通过隔离结构与像素电极和光电导层隔离。

3. 发明授权

US07528438B2 Non-volatile memory including assist gate 有权
标题翻译：包括辅助门的非易失性存储器
公开(公告)号：US07528438B2
公开(公告)日：2009-05-05
申请号：US11162035
申请日：2005-08-26
申请人： Ko-Hsing Chang , Chiu-Tsung Huang
发明人： Ko-Hsing Chang , Chiu-Tsung Huang
IPC分类号： H01L29/788 , H01L29/76
CPC分类号： G11C16/0491 , G11C16/0425 , H01L27/115 , H01L27/11521 , H01L29/42328
摘要： A non-volatile memory is provided. An assist gate structure is formed on a substrate such that the width at the bottom of the assist gate structure is greater than the width at the top of the assist gate structure. A floating gate is formed on one side of the assist gate structure and disposed between a word line and the substrate. The width at the bottom of the floating gate is smaller than the width at the top of the floating gate. The word line, the floating gate and the assist gate structure together form a memory unit. A tunneling dielectric layer is formed between the floating gate and the substrate. An inter-gate dielectric layer is formed between the word line, the floating gate and the assist gate structure. Source/drain regions are formed in the substrate on the respective sides of the memory unit.
摘要翻译：提供非易失性存储器。辅助栅极结构形成在基板上，使得辅助栅极结构底部的宽度大于辅助栅极结构顶部的宽度。浮动栅极形成在辅助栅极结构的一侧并且设置在字线和基板之间。浮动栅极底部的宽度小于浮动栅极顶部的宽度。字线，浮栅和辅助栅结构一起形成存储单元。在浮动栅极和衬底之间形成隧穿电介质层。在字线，浮栅和辅助栅结构之间形成栅极间电介质层。源极/漏极区域形成在存储器单元的相应侧上的衬底中。

4. 发明申请

US20060186459A1 NON-VOLATILE MEMORY AND MANUFACTURING METHOD THEREOF 有权
标题翻译：非易失性存储器及其制造方法
公开(公告)号：US20060186459A1
公开(公告)日：2006-08-24
申请号：US11162035
申请日：2005-08-26
申请人： Ko-Hsing Chang , Chiu-Tsung Huang
发明人： Ko-Hsing Chang , Chiu-Tsung Huang
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： G11C16/0491 , G11C16/0425 , H01L27/115 , H01L27/11521 , H01L29/42328
摘要： A non-volatile memory is provided. An assist gate structure is formed on a substrate such that the width at the bottom of the assist gate structure is greater than the width at the top of the assist gate structure. A floating gate is formed on one side of the assist gate structure and disposed between a word line and the substrate. The width at the bottom of the floating gate is smaller than the width at the top of the floating gate. The word line, the floating gate and the assist gate structure together form a memory unit. A tunneling dielectric layer is formed between the floating gate and the substrate. An inter-gate dielectric layer is formed between the word line, the floating gate and the assist gate structure. Source/drain regions are formed in the substrate on the respective sides of the memory unit.
摘要翻译：提供非易失性存储器。辅助栅极结构形成在基板上，使得辅助栅极结构底部的宽度大于辅助栅极结构顶部的宽度。浮动栅极形成在辅助栅极结构的一侧并且设置在字线和基板之间。浮动栅极底部的宽度小于浮动栅极顶部的宽度。字线，浮栅和辅助栅结构一起形成存储单元。在浮动栅极和衬底之间形成隧穿电介质层。在字线，浮栅和辅助栅结构之间形成栅极间电介质层。源极/漏极区域形成在存储器单元的相应侧上的衬底中。

5. 发明申请

US20090161406A1 NON-VOLATILE MEMORY AND METHOD FOR FABRICATING THE SAME 审中-公开
标题翻译：非易失性存储器及其制造方法
公开(公告)号：US20090161406A1
公开(公告)日：2009-06-25
申请号：US12054393
申请日：2008-03-25
申请人： Jen-Chi Chuang , Chiu-Tsung Huang , Yu-Chieh Liao
发明人： Jen-Chi Chuang , Chiu-Tsung Huang , Yu-Chieh Liao
IPC分类号： G11C11/36 , H01L21/06 , G11C11/00
CPC分类号： H01L27/1021 , G11C13/0004 , H01L27/24
摘要： A non-volatile memory including a diode and a memory cell is described. The diode includes a doped region, a metal silicide layer, and a patterned doped semiconductor layer. The doped region of a first conductive type is formed in a substrate. The metal silicide layer is formed on the substrate. The patterned doped semiconductor layer of a second conductive type is formed on the metal silicide layer. The memory cell is formed on the substrate and coupled with the diode.
摘要翻译：描述包括二极管和存储单元的非易失性存储器。二极管包括掺杂区域，金属硅化物层和图案化掺杂半导体层。第一导电类型的掺杂区域形成在衬底中。金属硅化物层形成在基板上。在金属硅化物层上形成第二导电类型的图案化掺杂半导体层。存储单元形成在衬底上并与二极管耦合。

6. 发明申请

US20050145919A1 [MULTI-LEVEL MEMORY CELL] 失效
标题翻译： [多级记忆体]
公开(公告)号：US20050145919A1
公开(公告)日：2005-07-07
申请号：US10707677
申请日：2004-01-02
申请人： Ko-Hsing Chang , Chiu-Tsung Huang
发明人： Ko-Hsing Chang , Chiu-Tsung Huang
IPC分类号： H01L21/28 , H01L21/336 , H01L29/792 , H01L29/76
CPC分类号： H01L29/66833 , H01L21/28282 , H01L29/7923
摘要： A multi-level memory cell including a substrate, a tunneling dielectric layer, a charge-trapping layer, a top dielectric layer, a gate and a pair of source/drain regions is provided. The tunneling dielectric layer, the charge-trapping layer and the top dielectric layer are sequentially formed between the substrate and the gate. The top dielectric layer has at least two portions, and the top dielectric layer in each portion has a different thickness. The source/drain regions are disposed in the substrate on each side of the gate. Since the thickness of the top dielectric layer in each portion is different, the electric field strength between the gate and the substrate when a voltage is applied to the memory cell are different in each portion. With the number of charges trapped within the charge-trapping layer different in each portion, a multiple of data bits can be stored within each memory cell.
摘要翻译：提供了包括衬底，隧道电介质层，电荷俘获层，顶部电介质层，栅极和一对源极/漏极区域的多层存储单元。隧道介电层，电荷俘获层和顶部电介质层依次形成在基板和栅极之间。顶部电介质层具有至少两个部分，并且每个部分中的顶部电介质层具有不同的厚度。源极/漏极区域设置在栅极的每一侧的衬底中。由于各部分的顶部电介质层的厚度不同，所以当向存储单元施加电压时，栅极与衬底之间的电场强度各不相同。由于每个部分中的电荷俘获层内陷入的电荷数量不同，所以可以在每个存储单元内存储多个数据位。

7. 发明申请

US20050029590A1 SILICON-ON-INSULATOR DEVICE STRUCTURE 失效
标题翻译：绝缘体绝缘体器件结构
公开(公告)号：US20050029590A1
公开(公告)日：2005-02-10
申请号：US10711624
申请日：2004-09-29
申请人： Chiu-Tsung Huang , Ke-Kung Liao , Jen-Chi Chung , Li-Lun Chi
发明人： Chiu-Tsung Huang , Ke-Kung Liao , Jen-Chi Chung , Li-Lun Chi
IPC分类号： H01L21/84 , H01L27/12 , H01L29/76 , H01L29/786
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/78612
摘要： A silicon-on-insulator device structure having a silicon-on-insulator substrate, a transistor and a control transistor is provided. The transistor and the control transistor are disposed on the silicon-on-insulator substrate. The transistor and the control transistor share a common source region. The drain region of the transistor is electrically connected to the main body of the transistor. By forming of a control transistor between the source terminal and the main body of the transistor and switching the control transistor on or off on demand, the silicon-on-insulator device embodies the advantages of both floating-body effect and body-tied characteristic.
摘要翻译：提供了具有绝缘体上硅衬底，晶体管和控制晶体管的绝缘体上硅器件结构。晶体管和控制晶体管设置在绝缘体上硅衬底上。晶体管和控制晶体管共享共同的源极区域。晶体管的漏极区域电连接到晶体管的主体。通过在晶体管的源极端子和主体之间形成控制晶体管，并根据需要开启或关闭控制晶体管，绝缘体上的器件体现了浮体效应和身体结合特性两者的优点。

8. 发明授权

US07465632B2 Method for forming buried doped region 有权
标题翻译：用于形成掩埋掺杂区的方法
公开(公告)号：US07465632B2
公开(公告)日：2008-12-16
申请号：US11163728
申请日：2005-10-28
申请人： Chiu-Tsung Huang , Su-Yuan Chang
发明人： Chiu-Tsung Huang , Su-Yuan Chang
IPC分类号： H01L21/336
CPC分类号： H01L21/74 , H01L21/26513
摘要： A method for forming a buried doped region is provided. A first insulating layer is formed on a substrate and the first insulating layer is patterned to from an opening that extends in a first direction. A buried doped region is formed in the substrate exposed by the opening. Thereafter, a second insulating layer is formed on the substrate to fill the opening. The second insulating layer together with the first insulation layer form a third insulating layer. The third insulating layer is patterned to form an isolation layer that exposes the substrate and the buried doped region. The isolation layer extends in a second direction and crosses over the first direction. A semiconductor layer is formed on the substrate to fill the areas on the respective sides of the isolation layer.
摘要翻译：提供一种形成掩埋掺杂区域的方法。第一绝缘层形成在基板上，并且第一绝缘层从沿第一方向延伸的开口图案化。在由开口暴露的衬底中形成掩埋掺杂区域。此后，在基板上形成第二绝缘层以填充开口。第二绝缘层与第一绝缘层一起形成第三绝缘层。将第三绝缘层图案化以形成暴露衬底和掩埋掺杂区域的隔离层。隔离层在第二方向上延伸并跨过第一方向。在衬底上形成半导体层以填充隔离层的相应侧面上的区域。

9. 发明申请

US20060128102A1 MANUFACTURING METHOD OF AN NON-VOLATILE MEMORY CELL 审中-公开
标题翻译：非挥发性记忆细胞的制造方法
公开(公告)号：US20060128102A1
公开(公告)日：2006-06-15
申请号：US11307548
申请日：2006-02-13
申请人： Ko-Hsing Chang , Chiu-Tsung Huang
发明人： Ko-Hsing Chang , Chiu-Tsung Huang
IPC分类号： H01L21/336
CPC分类号： H01L27/11568 , H01L27/115 , H01L29/792 , H01L29/7926
摘要： A manufacturing method of a non-volatile memory cell is provided. The non-volatile memory at least includes a substrate, a gate, a first source/drain region, a composite dielectric layer and a second source/drain region. A trench is formed in a substrate and a gate is formed inside the trench. The first source/drain region is formed at the bottom of the trench. The composite dielectric layer is formed between the gate and the surface of the trench. The composite dielectric layer includes at least a charge-trapping layer. The second source/drain region is formed in the substrate next to the sides of the gate.
摘要翻译：提供了一种非易失性存储单元的制造方法。非易失性存储器至少包括衬底，栅极，第一源极/漏极区域，复合电介质层和第二源极/漏极区域。在衬底中形成沟槽，并且在沟槽内形成栅极。第一源极/漏极区域形成在沟槽的底部。复合电介质层形成在沟槽的栅极和表面之间。复合介电层至少包括电荷捕获层。第二源极/漏极区域形成在栅极侧面旁边的衬底中。

10. 发明授权

US07056787B2 Method of manufacturing semiconductor device 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US07056787B2
公开(公告)日：2006-06-06
申请号：US10905610
申请日：2005-01-12
申请人： Ko-Hsing Chang , Chiu-Tsung Huang
发明人： Ko-Hsing Chang , Chiu-Tsung Huang
IPC分类号： H01L21/8242 , H01L21/20 , H01L21/4763
CPC分类号： H01L21/7681 , H01L21/76802 , H01L21/76808 , H01L23/5223 , H01L23/5226 , H01L23/53295 , H01L28/55 , H01L2924/0002 , H01L2924/00
摘要： A method of manufacturing a semiconductor device. The method comprises steps of providing a substrate having a first metal layer and a second metal layer formed thereon. A first dielectric layer, an etching stop layer having a first opening located above the first metal layer and a second opening located above the second metal layer and a second dielectric layer are formed sequentially. A portion of the first dielectric layer and a portion of the second dielectric layer are removed to form a first trench exposing the first metal layer. A capacitor dielectric layer is formed over the substrate. A third opening is formed in the capacitor dielectric layer. A portion of the second dielectric layer and a portion of the first dielectric layer exposed by the third opening are removed to form an opening. A metal layer is formed to fill out the first trench and the opening.
摘要翻译：一种制造半导体器件的方法。该方法包括提供具有形成在其上的第一金属层和第二金属层的基板的步骤。顺序地形成第一电介质层，具有位于第一金属层上方的第一开口和位于第二金属层上方的第二开口的蚀刻停止层和第二介电层。去除第一电介质层的一部分和第二电介质层的一部分以形成露出第一金属层的第一沟槽。在衬底上形成电容器电介质层。在电容器电介质层中形成第三开口。第二电介质层的一部分和被第三开口暴露的第一电介质层的一部分被去除以形成开口。形成金属层以填充第一沟槽和开口。

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