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1. 发明申请

US20120326265A1 METHOD OF FORMING MEMORY CELL ACCESS DEVICE 有权
标题翻译：形成记忆细胞存取装置的方法
公开(公告)号：US20120326265A1
公开(公告)日：2012-12-27
申请号：US13168753
申请日：2011-06-24
申请人： Erh-Kun Lai , Hsiang-Lan Lung , Edward Kiewra
发明人： Erh-Kun Lai , Hsiang-Lan Lung , Edward Kiewra
IPC分类号： H01L21/762 , H01L27/08 , B82Y99/00
CPC分类号： H01L27/1021 , H01L27/101
摘要： A memory device includes an access device including a first doped semiconductor region having a first conductivity type, and a second doped semiconductor region having a second conductivity type opposite the first conductivity type. Both the first and the second doped semiconductor regions are formed in a single-crystalline semiconductor body, and define a p-n junction between them. The first and second doped semiconductor regions are implemented in isolated parallel ridges formed in the single-crystal semiconductor body. Each ridge is crenellated, and the crenellations define semiconductor islands; the first doped semiconductor region occupies a lower portion of the islands and an upper part of the ridge, and the second doped semiconductor region occupies an upper portion of the islands, so that the p-n junctions are defined within the islands.
摘要翻译：存储器件包括一个存取器件，它包括具有第一导电类型的第一掺杂半导体区域和具有与第一导电类型相反的第二导电类型的第二掺杂半导体区域。第一掺杂半导体区域和第二掺杂半导体区域均形成在单晶半导体本体中，并且在它们之间限定p-n结。第一和第二掺杂半导体区域被实现在形成在单晶半导体本体中的隔离的平行脊中。每个山脊都是锯齿状的，扇形界定半岛; 第一掺杂半导体区域占据岛的下部和脊的上部，并且第二掺杂半导体区占据岛的上部，从而在岛内限定p-n结。

2. 发明授权

US08437192B2 3D two bit-per-cell NAND flash memory 有权
标题翻译： 3D双比特单元NAND闪存
公开(公告)号：US08437192B2
公开(公告)日：2013-05-07
申请号：US12785291
申请日：2010-05-21
申请人： Hsiang-Lan Lung , Hang-Ting Lue , Yen-Hao Shih , Erh-Kun Lai , Ming-Hsiu Lee , Tien-Yen Wang
发明人： Hsiang-Lan Lung , Hang-Ting Lue , Yen-Hao Shih , Erh-Kun Lai , Ming-Hsiu Lee , Tien-Yen Wang
IPC分类号： G11C16/00 , G11C16/02 , G11C16/04 , G11C5/02 , G11C5/06
CPC分类号： H01L27/11578 , G11C16/0483 , H01L27/11582 , H01L29/66833 , H01L29/7926
摘要： A 3D memory device includes bottom and top memory cubes having respective arrays of vertical NAND string structures. A common source plane comprising a layer of conductive material is between the top and bottom memory cubes. The source plane is supplied a bias voltage such as ground, and is selectively coupled to an end of the vertical NAND string structures of the bottom and top memory cubes. Memory cells in a particular memory cube are read using current through the particular vertical NAND string between the source plane and a corresponding bit line coupled to another end of the particular vertical NAND string.
摘要翻译： 3D存储器件包括具有垂直NAND串结构的相应阵列的底部和顶部存储立方体。包括导电材料层的共同源平面位于顶部和底部存储立方体之间。源平面被提供诸如地的偏置电压，并且选择性地耦合到底部和顶部存储立方体的垂直NAND串结构的一端。通过源平面与耦合到特定垂直NAND串的另一端的对应位线之间的特定垂直NAND串的电流来读取特定存储器立方体中的存储单元。

3. 发明授权

US08933536B2 Polysilicon pillar bipolar transistor with self-aligned memory element 有权
标题翻译：具有自对准存储元件的多晶硅柱双极晶体管
公开(公告)号：US08933536B2
公开(公告)日：2015-01-13
申请号：US12357912
申请日：2009-01-22
申请人： Hsiang-Lan Lung , Erh-Kun Lai , Chung H. Lam , Bipin Rajendran
发明人： Hsiang-Lan Lung , Erh-Kun Lai , Chung H. Lam , Bipin Rajendran
IPC分类号： H01L27/082 , H01L27/102 , H01L27/24 , H01L45/00
CPC分类号： H01L27/1026 , H01L27/2445 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/1246 , H01L45/142 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/1616 , H01L45/1625 , H01L45/1683
摘要： Memory cells having memory elements self-aligned with the emitters of bipolar junction transistor access devices are described herein, as well as methods for manufacturing such devices. A memory device as described herein comprises a plurality of memory cells. Memory cells in the plurality of memory cells include a bipolar junction transistor comprising an emitter comprising a pillar of doped polysilicon. The memory cells include an insulating element over the emitter and having an opening extending through the insulating layer, the opening centered over the emitter. The memory cells also include a memory element within the opening and electrically coupled to the emitter.
摘要翻译：本文描述了具有与双极结晶体管存取装置的发射极自对准的存储元件的存储单元以及用于制造这种装置的方法。如本文所述的存储器件包括多个存储器单元。多个存储单元中的存储单元包括双极结型晶体管，其包括由掺杂多晶硅柱构成的发射极。存储单元包括在发射器上的绝缘元件，并且具有延伸穿过绝缘层的开口，开口以发射器为中心。存储单元还包括在开口内的存储元件并电耦合到发射器。

4. 发明授权

US08310864B2 Self-aligned bit line under word line memory array 有权
标题翻译：字线内存阵列下的自对准位线
公开(公告)号：US08310864B2
公开(公告)日：2012-11-13
申请号：US12815680
申请日：2010-06-15
申请人： Hsiang-Lan Lung , Chung H Lam , Erh-Kun Lai , Matthew J. Breitwisch
发明人： Hsiang-Lan Lung , Chung H Lam , Erh-Kun Lai , Matthew J. Breitwisch
IPC分类号： G11C11/00
CPC分类号： H01L27/2454 , H01L27/2445 , H01L27/2472 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/142 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/148
摘要： A memory device is described that comprises a plurality of bit lines and an array of vertical transistors arranged on the plurality of bit lines. A plurality of word lines is formed along rows of vertical transistors in the array which comprise thin film sidewalls of word line material and arranged so that the thin film sidewalls merge in the row direction, and do not merge in the column direction, to form word lines. The word lines provide “surrounding gate” structures for embodiments in which the vertical transistors are field effect transistors. Memory elements are formed in electrical communication with the vertical transistors. A fully self-aligned process is provided in which the word lines and memory elements are aligned with the vertical transistors without additional patterning steps.
摘要翻译：描述了包括多个位线和布置在多个位线上的垂直晶体管阵列的存储器件。多个字线沿阵列中的垂直晶体管行形成，其中包括字线材料的薄膜侧壁，并且布置成使得薄膜侧壁在行方向上合并，并且不在列方向上合并，以形成字线条。对于其中垂直晶体管是场效应晶体管的实施例，字线提供周围的栅极结构。存储元件形成为与垂直晶体管电连通。提供了完全自对准的工艺，其中字线和存储元件与垂直晶体管对准，而没有额外的图案化步骤。

5. 发明授权

US08093661B2 Integrated circuit device with single crystal silicon on silicide and manufacturing method 有权
标题翻译：硅化硅单晶硅集成电路器件及其制造方法
公开(公告)号：US08093661B2
公开(公告)日：2012-01-10
申请号：US12349903
申请日：2009-01-07
申请人： Hsiang-Lan Lung , Erh-Kun Lai
发明人： Hsiang-Lan Lung , Erh-Kun Lai
IPC分类号： H01L29/86 , H01L21/334
CPC分类号： H01L27/1021 , H01L21/743 , H01L27/105 , H01L29/7827 , H01L29/861
摘要： A silicide element separates a single crystal silicon node from an underlying silicon substrate, and is capable of acting as a conductive element for interconnecting devices on the device. The single crystal silicon node can act as one terminal of a diode, and a second semiconductor node on top of it can act as the other terminal of the diode. The single crystal silicon node can act as one of the terminals of the transistor, and second and third semiconductor nodes are formed in series on top of it, providing a vertical transistor structure, which can be configured as a field effect transistor or bipolar junction transistor. The silicide element can be formed by a process that consumes a base of a protruding single crystal element by silicide formation processes, while shielding upper portions of the protruding element from the silicide formation process.
摘要翻译：硅化物元件将单晶硅节点与底层硅衬底分开，并且能够用作用于互连器件上的器件的导电元件。单晶硅节点可以作为二极管的一个端子，其顶部的第二个半导体节点可以作为二极管的另一个端子。单晶硅节点可以用作晶体管的端子之一，并且第二和第三半导体节点在其顶部上串联形成，提供垂直晶体管结构，其可被配置为场效应晶体管或双极结型晶体管。硅化物元件可以通过利用硅化物形成工艺消耗突出的单晶元件的基底，同时屏蔽突出元件的上部从硅化物形成工艺形成的工艺。

6. 发明授权

US08089137B2 Integrated circuit memory with single crystal silicon on silicide driver and manufacturing method 有权
标题翻译：集成电路存储器采用单晶硅硅化硅驱动器及制造方法
公开(公告)号：US08089137B2
公开(公告)日：2012-01-03
申请号：US12349874
申请日：2009-01-07
申请人： Hsiang-Lan Lung , Erh-Kun Lai
发明人： Hsiang-Lan Lung , Erh-Kun Lai
IPC分类号： H01L27/10 , H01L29/861 , H01L21/324
CPC分类号： H01L45/1675 , G11C13/0004 , G11C2213/72 , H01L27/1021 , H01L27/2409 , H01L27/2463 , H01L45/04 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/142 , H01L45/144 , H01L45/146 , H01L45/147 , H01L45/1625 , H01L45/1641 , H01L45/1683
摘要： A memory device includes a diode driver and a data storage element, such as an element comprising phase change memory material, and in which the diode driver comprises a silicide element on a silicon substrate with a single crystal silicon node on the silicide element. The silicide element separates the single crystal silicon node from the underlying silicon substrate, preventing the flow of carriers from the single crystal silicon node into the substrate, and is capable of acting as a conductive element for interconnecting devices on the device. The single crystal silicon node acts as one terminal of a diode, and a second semiconductor node is formed on top of it, acting as the other terminal of the diode.
摘要翻译：存储器件包括二极管驱动器和诸如包括相变存储器材料的元件的数据存储元件，并且其中二极管驱动器在硅衬底上包括在硅化物元件上具有单晶硅节点的硅化物元件。硅化物元件将单晶硅节点与下面的硅衬底分开，防止载体从单晶硅节点流入衬底，并且能够用作用于互连器件上的器件的导电元件。单晶硅节点用作二极管的一个端子，第二半导体节点形成在二极管的顶部，充当二极管的另一个端子。

7. 发明授权

US08030635B2 Polysilicon plug bipolar transistor for phase change memory 有权
标题翻译：用于相变存储器的多晶硅插头双极晶体管
公开(公告)号：US08030635B2
公开(公告)日：2011-10-04
申请号：US12353219
申请日：2009-01-13
申请人： Hsiang-Lan Lung , Erh-Kun Lai , Bipin Rajendran , Chung Hon Lam
发明人： Hsiang-Lan Lung , Erh-Kun Lai , Bipin Rajendran , Chung Hon Lam
IPC分类号： H01L29/02
CPC分类号： H01L45/04 , G11C13/0004 , H01L27/1026 , H01L27/2445 , H01L27/2463 , H01L45/06 , H01L45/085 , H01L45/1233 , H01L45/142 , H01L45/144 , H01L45/146 , H01L45/1625 , H01L45/1641 , H01L45/1675 , H01L45/1683
摘要： Memory devices and methods for manufacturing are described herein. A memory device described herein includes a plurality of memory cells. Memory cells in the plurality of memory cells comprise respective bipolar junction transistors and memory elements. The bipolar junction transistors are arranged in a common collector configuration and include an emitter comprising doped polysilicon having a first conductivity type, the emitter contacting a corresponding word line in a plurality of word lines to define a pn junction. The bipolar junction transistors include a portion of the corresponding word line underlying the emitter acting as a base, and a collector comprising a portion of the single-crystalline substrate underlying the base.
摘要翻译：本文描述了存储器件和制造方法。本文描述的存储器件包括多个存储器单元。多个存储单元中的存储单元包括相应的双极结型晶体管和存储元件。双极结晶体管被布置成共同的集电极配置，并且包括发射器，其包括具有第一导电类型的掺杂多晶硅，发射极与多个字线中的对应字线接触以限定pn结。双极结晶体管包括作为基极的发射极下面的相应字线的一部分，以及包含基底下方的单晶衬底的一部分的集电极。

8. 发明授权

US09019771B2 Dielectric charge trapping memory cells with redundancy 有权
标题翻译：介质电荷捕获具有冗余的存储单元
公开(公告)号：US09019771B2
公开(公告)日：2015-04-28
申请号：US13661723
申请日：2012-10-26
申请人： Hsiang-Lan Lung , Yen-Hao Shih , Erh-Kun Lai , Ming-Hsiu Lee
发明人： Hsiang-Lan Lung , Yen-Hao Shih , Erh-Kun Lai , Ming-Hsiu Lee
IPC分类号： G11C16/06 , G11C16/04 , G11C16/10
CPC分类号： G11C16/0475 , G11C16/10
摘要： A memory cell array of dielectric charge trapping memory cells and method for performing program, read and erase operations on the memory cell array that includes bits stored at charge trapping sites in adjacent memory cells. A bit of information is stored at a first charge trapping site in a first memory cell and a second charge trapping site in a second adjacent memory cell. Storing charge at two trapping sites in adjacent memory cells increases data retention rates of the array of memory cells as each charge trapping site can be read to represent the data that is stored at the data site. Each corresponding charge trapping site can be read independently and in parallel so that the results can be compared to determine the data value that is stored at the data site in an array of dielectric charge trapping memory cells.
摘要翻译：介质电荷俘获存储器单元的存储单元阵列和用于对存储在相邻存储器单元中的电荷俘获位置处存储的位的存储单元阵列执行编程，读取和擦除操作的方法。一些信息存储在第一存储单元中的第一电荷捕获位点和第二相邻存储单元中的第二电荷捕获位点。在相邻存储器单元中的两个捕获位置处存储电荷增加了存储器单元阵列的数据保留率，因为可以读取每个电荷捕获位点以表示存储在数据站点的数据。可以独立地并行地读取每个对应的电荷俘获位点，以便比较结果以确定存储在介电电荷俘获存储器单元阵列中的数据位置处的数据值。

9. 发明申请

US20140119127A1 DIELECTRIC CHARGE TRAPPING MEMORY CELLS WITH REDUNDANCY 有权
标题翻译：具有冗余性的电介质电荷捕获记忆细胞
公开(公告)号：US20140119127A1
公开(公告)日：2014-05-01
申请号：US13661723
申请日：2012-10-26
申请人： Hsiang-Lan Lung , YEN-HAO SHIH , ERH-KUN LAI , MING-HSIU LEE
发明人： Hsiang-Lan Lung , YEN-HAO SHIH , ERH-KUN LAI , MING-HSIU LEE
IPC分类号： G11C16/06
CPC分类号： G11C16/0475 , G11C16/10
摘要： A memory cell array of dielectric charge trapping memory cells and method for performing program, read and erase operations on the memory cell array that includes bits stored at charge trapping sites in adjacent memory cells. A bit of information is stored at a first charge trapping site in a first memory cell and a second charge trapping site in a second adjacent memory cell. Storing charge at two trapping sites in adjacent memory cells increases data retention rates of the array of memory cells as each charge trapping site can be read to represent the data that is stored at the data site. Each corresponding charge trapping site can be read independently and in parallel so that the results can be compared to determine the data value that is stored at the data site in an array of dielectric charge trapping memory cells.
摘要翻译：介质电荷俘获存储器单元的存储单元阵列和用于对存储在相邻存储器单元中的电荷俘获位置处存储的位的存储单元阵列执行编程，读取和擦除操作的方法。一些信息存储在第一存储单元中的第一电荷捕获位点和第二相邻存储单元中的第二电荷捕获位点。在相邻存储器单元中的两个捕获位置处存储电荷增加了存储器单元阵列的数据保留率，因为可以读取每个电荷捕获位点以表示存储在数据站点的数据。可以独立地并行地读取每个对应的电荷俘获位点，以便比较结果以确定存储在介电电荷俘获存储器单元阵列中的数据位置处的数据值。

10. 发明授权

US08426294B2 3D memory array arranged for FN tunneling program and erase 有权
标题翻译： 3D存储阵列用于FN隧道编程和擦除
公开(公告)号：US08426294B2
公开(公告)日：2013-04-23
申请号：US13476964
申请日：2012-05-21
申请人： Hsiang-Lan Lung , Yen-Hao Shih , Erh-Kun Lai , Ming-Hsiu Lee , Hang-Ting Lue
发明人： Hsiang-Lan Lung , Yen-Hao Shih , Erh-Kun Lai , Ming-Hsiu Lee , Hang-Ting Lue
IPC分类号： H01L29/76
CPC分类号： G11C16/0458 , H01L27/0688 , H01L27/10 , H01L27/11578 , H01L27/11582
摘要： A 3D memory device includes an array of semiconductor body pillars and bit line pillars, dielectric charge trapping structures, and a plurality of levels of word line structures arranged orthogonally to the array of semiconductor body pillars and bit line pillars. The semiconductor body pillars have corresponding bit line pillars on opposing first and second sides, providing source and drain terminals. The semiconductor body pillars have first and second channel surfaces on opposing third and fourth sides. Dielectric charge trapping structures overlie the first and second channel surfaces, providing data storage sites on two sides of each semiconductor body pillar in each level of the 3D array. The device can be operated as a 3D AND-decoded flash memory.
摘要翻译： 3D存储器件包括半导体主体柱和位线柱的阵列，介电电荷俘获结构以及与半导体主体柱和位线柱阵列垂直布置的多个字线结构。半导体主体柱在相对的第一和第二侧上具有对应的位线柱，提供源极和漏极端子。半导体主体支柱在相对的第三和第四侧上具有第一和第二通道表面。电介质电荷捕获结构覆盖在第一和第二通道表面上，在3D阵列的每个级别中的每个半导体主体支柱的两侧提供数据存储位置。该设备可以作为3D和解码的闪存操作。

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