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1. 发明授权

US5329179A Arrangement for parallel programming of in-system programmable IC logical devices 失效
标题翻译：系统可编程IC逻辑器件的并行编程布置
公开(公告)号：US5329179A
公开(公告)日：1994-07-12
申请号：US957311
申请日：1992-10-05
申请人： Howard Tang , Cyrus Tsui
发明人： Howard Tang , Cyrus Tsui
IPC分类号： G06F17/50 , H03K19/177
CPC分类号： G06F17/5054
摘要： A plurality of programmable logic devices are connected in parallel to a programming command generator. A device selector connects individual devices with the programming command generator, thereby permitting the individual devices to be programmed without routing the programming data through other devices. In an alternative embodiment, an identification code is used to place the individual device in a condition to receive programming data. Using the teachings of this invention, programming data may initially be entered into a plurality of devices, and then the data entered in all the devices may be used to program the devices simultaneously. This procedure requires less time than entering data and giving each device the execute command in sequence.
摘要翻译：多个可编程逻辑器件并行连接到编程命令发生器。设备选择器将各个设备与编程命令发生器连接，从而允许编程各个设备，而不通过其他设备路由编程数据。在替代实施例中，使用识别码将单个设备置于接收节目数据的状态。使用本发明的教导，编程数据可以最初被输入到多个设备中，然后可以使用在所有设备中输入的数据来同时对设备进行编程。该过程比输入数据需要更少的时间，并且每个设备按顺序给出执行命令。

2. 发明授权

US06828823B1 Non-volatile and reconfigurable programmable logic devices 有权
标题翻译：非易失性和可重新配置的可编程逻辑器件
公开(公告)号：US06828823B1
公开(公告)日：2004-12-07
申请号：US10439602
申请日：2003-05-16
申请人： Cyrus Tsui , Benny Ma , Om P. Agrawal , Ju Shen , Sam Tsai , Jack Wong , Chan-Chi Jason Cheng
发明人： Cyrus Tsui , Benny Ma , Om P. Agrawal , Ju Shen , Sam Tsai , Jack Wong , Chan-Chi Jason Cheng
IPC分类号： H03K19177
CPC分类号： H03K19/17752 , H03K19/1776 , H03K19/17768
摘要： An integrated circuit includes non-volatile and volatile memory, with the volatile memory controlling the integrated circuit's functionality. Various techniques are disclosed for programming the different types of memory through one or more data ports to provide in-system programmability and dynamic reconfigurability. External configuration devices are not required if the data from the non-volatile memory is transferred directly to the volatile memory.
摘要翻译：集成电路包括非易失性和易失性存储器，易失性存储器控制集成电路的功能。公开了用于通过一个或多个数据端口对不同类型的存储器进行编程以提供系统内可编程性和动态可重构性的各种技术。如果来自非易失性存储器的数据直接传输到易失性存储器，则不需要外部配置设备。

3. 发明授权

US5130574A Programmable logic device providing product term sharing and steering to the outputs of the programmable logic device 失效
标题翻译：可编程逻辑器件提供产品术语共享和转向可编程逻辑器件的输出
公开(公告)号：US5130574A
公开(公告)日：1992-07-14
申请号：US696461
申请日：1991-05-06
申请人： Ju Shen , Albert L. Chan , Kapil Shankar , Cyrus Tsui
发明人： Ju Shen , Albert L. Chan , Kapil Shankar , Cyrus Tsui
IPC分类号： H03K19/177
CPC分类号： H03K19/17708
摘要： A programmable logic device is disclosed which includes a programmable AND array, a plurality of logic circuits connected to groups of product term outputs from the AND array for performing a logical OR operation of the product term inputs and the programmable logic device includes programmable OR circuitry for selectively connecting one or more of the ORed groups of product terms to one or more outputs of the programmable logic device. The programmable OR circuit permits product term steering and sharing.
摘要翻译：公开了一种可编程逻辑器件，其包括可编程AND阵列，多个逻辑电路连接到来自AND阵列的产品项输出组，用于执行产品项输入的逻辑或运算，并且可编程逻辑器件包括可编程OR电路选择性地将一个或多个OR组的产品术语连接到可编程逻辑器件的一个或多个输出。可编程OR电路允许产品术语转向和共享。

4. 发明授权

US4670708A Short detector for fusible link array using a pair of parallel connected reference fusible links 失效
标题翻译：使用一对并联连接的参考熔断链路的易熔链路阵列的短检测器
公开(公告)号：US4670708A
公开(公告)日：1987-06-02
申请号：US635861
申请日：1984-07-30
申请人： Bob Bosnyak , Albert Chan , Mark Fitzpatrick , Gary Gouldsberry , Cyrus Tsui , Andrew K. Chan
发明人： Bob Bosnyak , Albert Chan , Mark Fitzpatrick , Gary Gouldsberry , Cyrus Tsui , Andrew K. Chan
IPC分类号： G11C29/00 , G01R31/02 , G11C17/00 , G11C29/02 , G11C29/04 , G11C29/50
CPC分类号： G11C29/50008 , G01R31/025 , G11C29/02 , G11C29/50 , G11C17/14
摘要： Circuitry is provided for testing fusible link arrays for short circuits around the fusible links. Each link is electrically isolated and compared with a pair of reference fusible links to detect the presence or absence of a short circuit.
摘要翻译：提供电路用于测试易熔链路周围短路的易熔链路阵列。每个链路都是电隔离的，并与一对基准可熔链路进行比较，以检测短路的存在与否。

5. 发明授权

US4634898A TTL buffer circuit incorporating active pull-down transistor 失效
标题翻译：包含有源下拉晶体管的TTL缓冲电路
公开(公告)号：US4634898A
公开(公告)日：1987-01-06
申请号：US554474
申请日：1983-11-22
申请人： Gary Gouldsberry , Albert Chan , Cyrus Tsui , Mark Fitzpatrick
发明人： Gary Gouldsberry , Albert Chan , Cyrus Tsui , Mark Fitzpatrick
IPC分类号： H03K19/013 , H03K19/088 , H03K17/04 , H03K17/60
CPC分类号： H03K19/013 , H03K19/0136 , H03K19/088
摘要： A unique double inversion buffer has a first means to invert and isolate the digital input signal, a second means to reinvert and further isolate the input signal, and an output means including an output transistor 94. The double inversion buffer is configured with active pull-down means on the output transistor 92. The high-to-low propagation delay time and the low-to-high propagation delay times through the double inversion buffer and reduced by use of the active pull-down means. Rapid turnoff of the output transistor is accomplished by coupling a transistor to its base to instantaneously turn it off. In a preferred embodiment, a clamping circuit 201 is used to hold the output voltage at a maximum predetermined level to further reduce the time it takes to reduce the output voltage to the logical "0" state.
摘要翻译：独特的双反相缓冲器具有第一装置，用于反转和隔离数字输入信号，第二装置重新转换并进一步隔离输入信号，以及包括输出晶体管94的输出装置。双反相缓冲器配置有主动上拉电阻，输出晶体管92的下降装置。通过双重反转缓冲器的高到低的传播延迟时间和低到高的传播延迟时间通过使用有源下拉装置而减少。输出晶体管的快速关断是通过将晶体管耦合到其基极来实时地将其截止的。在优选实施例中，钳位电路201用于将输出电压保持在最大预定电平，以进一步减少将输出电压降低到逻辑“0”状态所花费的时间。

6. 发明授权

US5191243A Output logic macrocell with enhanced functional capabilities 失效
标题翻译：具有增强功能的输出逻辑MACROCELL
公开(公告)号：US5191243A
公开(公告)日：1993-03-02
申请号：US696907
申请日：1991-05-06
申请人： Ju Shen , Albert L. Chan , Kapil Shankar , Cyrus Tsui
发明人： Ju Shen , Albert L. Chan , Kapil Shankar , Cyrus Tsui
IPC分类号： H03K19/173 , H03K19/21
CPC分类号： H03K19/1736
摘要： An output logic macrocell ("OLMC") containing an exclusive OR gate is associated with the product terms and other outputs of a logic block such as a programmable logic array. The OLMC is capable of providing enhanced functions, including cascaded exclusive OR gates, function sharing, T and J-K flip-flop emulation, asynchronous clocking, and a reset selection. In addition, a logic block is used as the source of an asynchronous clock pulse and is connected to the global clock distribution system of a device such as a high density programmable logic device.
摘要翻译：包含异或门的输出逻辑宏单元（“OLMC”）与诸如可编程逻辑阵列之类的逻辑块的乘积项和其它输出相关联。 OLMC能够提供增强的功能，包括级联异或门，功能共享，T和J-K触发器仿真，异步时钟和复位选择。此外，逻辑块用作异步时钟脉冲的源，并连接到诸如高密度可编程逻辑器件的器件的全局时钟分配系统。

7. 发明授权

US4684830A Output circuit for a programmable logic array 失效
标题翻译：可编程逻辑阵列的输出电路
公开(公告)号：US4684830A
公开(公告)日：1987-08-04
申请号：US715214
申请日：1985-03-22
申请人： Cyrus Tsui , Andrew K. L. Chan , Albert Chan , Mark E. Fitzpatrick , Zahid Ansari
发明人： Cyrus Tsui , Andrew K. L. Chan , Albert Chan , Mark E. Fitzpatrick , Zahid Ansari
IPC分类号： H03K19/177 , H03K19/20
CPC分类号： H03K19/17716
摘要： An output circuit (50) is provided for a programmable logic array (PLA) integrated circuit. The output circuit (50) includes a flip flop (52) which stores a given output term from the array. The flip flop (52) contains a set input lead (S) and a reset input lead (R). The signals present at the set input, reset input, the clock leads are generated by programmable logic within the PLA. A multiplexer (54) is provided which receives the output data of the flip flop (52) and the signal constituting the input data for the flip flop. The multiplexer provides the data input signal on the multiplexer output lead (60) when both the set and reset input signals are true. However, if either or both the set and reset input signals are false, then the multiplexer (54) provides the Q output signal from the flip flop (52) on the multiplexer output lead (60). The multiplexer output signal is presented to a three-state buffer (62) which in turn drives an output pin.
摘要翻译：为可编程逻辑阵列（PLA）集成电路提供输出电路（50）。输出电路（50）包括一个触发器（52），该触发器存储来自阵列的给定的输出项。触发器（52）包含设定输入引线（S）和复位输入引线（R）。存在于设定输入，复位输入，时钟引脚的信号由PLA内的可编程逻辑产生。提供了多路复用器（54），其接收触发器（52）的输出数据和构成触发器的输入数据的信号。当设置和复位输入信号都为真时，多路复用器在多路复用器输出引线（60）上提供数据输入信号。然而，如果设置和复位输入信号中的任何一个或两者都为假，则多路复用器（54）从多路复用器输出引线（60）上的触发器（52）提供Q输出信号。复用器输出信号被呈现给三态缓冲器（62），其又驱动输出引脚。

8. 发明授权

US4654830A Method and structure for disabling and replacing defective memory in a PROM 失效
标题翻译：用于禁用和替换PROM中的有缺陷的存储器的方法和结构
公开(公告)号：US4654830A
公开(公告)日：1987-03-31
申请号：US675379
申请日：1984-11-27
申请人： H. T. Chua , Cyrus Tsui , Albert Chan , Gary Gouldsberry
发明人： H. T. Chua , Cyrus Tsui , Albert Chan , Gary Gouldsberry
IPC分类号： G11C7/00 , G11C29/00 , G11C29/04 , G11C13/00
CPC分类号： G11C29/78
摘要： Means are provided for replacing a defective row (or column) of memory in a fuse-array PROM which comprises disabling the defective row and programming a redundant row to respond to the address of the defective row. Means are also provided for reducing the swing between high and low address voltages.The redundant row is connected via an AND gate through fuses to all ADDRESS and ADDRESS lines of the address buffer, so that the redundant row is always off until programmed. If a defective row is found, all memory cells in the defective row are disabled and the redundant row is programmed by selectively blowing fuses leading to the ADDRESS and ADDRESS lines thus causing the redundant row to respond to the address of the defective row.
摘要翻译：提供了用于替换熔丝阵列PROM中的存储器的有缺陷行（或列）的装置，其包括禁用缺陷行并编程冗余行以响应缺陷行的地址。还提供了用于减小高和低地址电压之间的摆动的装置。冗余行通过保险丝通过与门连接到地址缓冲区的所有ADDRESS和＆Upbar＆AS /线，以便冗余行始终关闭，直到编程为止。如果找到有缺陷的行，则有缺陷的行中的所有存储单元被禁用，并且冗余行被编程，通过选择性地吹送导致ADDRESS和＆amp; upbar＆AS /线的熔丝，从而使得冗余行响应缺陷行的地址。

9. 发明授权

US4638189A Fast and gate with programmable output polarity 失效
标题翻译：快速和门极可编程输出
公开(公告)号：US4638189A
公开(公告)日：1987-01-20
申请号：US626377
申请日：1984-06-29
申请人： George Geannopoulos , Cyrus Tsui , Mark Fitzpatrick , Andy Chan
发明人： George Geannopoulos , Cyrus Tsui , Mark Fitzpatrick , Andy Chan
IPC分类号： H03K19/177 , H03K17/66 , H03K19/173 , H03K19/20 , G06F11/28 , H03K19/003 , H03K19/082
CPC分类号： H03K19/1736 , H03K17/666
摘要： The present invention combines in either a logical AND function of N logical input signals, where N is a selected positive integer greater than or equal to 1, and provides programmably, either a direct AND output signal or a NAND output signal. The invention accomplishes this using a minimum number of components in the data path, between the logical input leads and logical output leads. A minimum of components in the data path reduces the propagation delay introduced by the circuit. The invention accomplishes this by providing two AND gates connected to the same set of N logical input signals. The output signal of one AND gate is inverted by an inverter with an enable/disable input lead. The output signal of the other AND gate is inverted twice by two inverters. The second inverter has an enable/disable input lead. Means are provided for exclusively enabling one or the other of the two inverters with an enable/disable input lead. Thus, either the once inverted signal is provided to the output lead or the twice inverted signal is provided to the output lead.
摘要翻译：本发明以N逻辑输入信号的逻辑和功能组合，其中N是大于或等于1的选择的正整数，并且可编程地提供直接AND输出信号或NAND输出信号。本发明使用数据路径中的最小数量的组件，逻辑输入引线和逻辑输出引线之间来实现。数据路径中的最小组件减少了由电路引入的传播延迟。本发明通过提供连接到同一组N个逻辑输入信号的两个与门来实现这一点。一个与门的输出信号由具有使能/禁止输入引线的反相器反相。另一个与门的输出信号由两个反相器反相两次。第二个反相器具有使能/禁止输入引线。提供了用于通过使能/禁止输入引线独占地使能两个逆变器中的一个或另一个的装置。因此，将一次反相信号提供给输出引线，或将两次反相信号提供给输出引线。

10. 发明授权

US07038490B1 Delay-matched ASIC conversion of a programmable logic device 有权
标题翻译：可编程逻辑器件的延迟匹配ASIC转换
公开(公告)号：US07038490B1
公开(公告)日：2006-05-02
申请号：US10660814
申请日：2003-09-12
申请人： Satwant Singh , Cyrus Tsui
发明人： Satwant Singh , Cyrus Tsui
IPC分类号： H01L25/00 , H03K19/177
CPC分类号： H03K19/177 , G06F17/505 , G06F17/5054 , H01L27/118
摘要： An ASIC conversion of a programmable logic device (PLD) is provided. The PLD includes a plurality of logic blocks coupled together by a PLD routing structure. The ASIC includes a plurality of logic blocks corresponding on a one-to-one basis with logic blocks in the PLD and a routing structure corresponding to the programmable routing structure of the PLD. Vias or traces are selectively placed in the ASIC so that logical behavior of its logic blocks matches that implemented in the PLD and the signal propagation delay through the ASIC matches the delay through the PLD.
摘要翻译：提供了可编程逻辑器件（PLD）的ASIC转换。 PLD包括通过PLD路由结构耦合在一起的多个逻辑块。 ASIC包括与PLD中的逻辑块一一对应的多个逻辑块，以及对应于PLD的可编程路由结构的路由结构。通常选择性地将放置在ASIC中的逻辑块的逻辑行为与PLD中实现的逻辑块匹配，并且通过ASIC的信号传播延迟与通过PLD的延迟匹配。

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