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    • 1. 发明授权
    • Output circuit for a programmable logic array
    • 可编程逻辑阵列的输出电路
    • US4684830A
    • 1987-08-04
    • US715214
    • 1985-03-22
    • Cyrus TsuiAndrew K. L. ChanAlbert ChanMark E. FitzpatrickZahid Ansari
    • Cyrus TsuiAndrew K. L. ChanAlbert ChanMark E. FitzpatrickZahid Ansari
    • H03K19/177H03K19/20
    • H03K19/17716
    • An output circuit (50) is provided for a programmable logic array (PLA) integrated circuit. The output circuit (50) includes a flip flop (52) which stores a given output term from the array. The flip flop (52) contains a set input lead (S) and a reset input lead (R). The signals present at the set input, reset input, the clock leads are generated by programmable logic within the PLA. A multiplexer (54) is provided which receives the output data of the flip flop (52) and the signal constituting the input data for the flip flop. The multiplexer provides the data input signal on the multiplexer output lead (60) when both the set and reset input signals are true. However, if either or both the set and reset input signals are false, then the multiplexer (54) provides the Q output signal from the flip flop (52) on the multiplexer output lead (60). The multiplexer output signal is presented to a three-state buffer (62) which in turn drives an output pin.
    • 为可编程逻辑阵列(PLA)集成电路提供输出电路(50)。 输出电路(50)包括一个触发器(52),该触发器存储来自阵列的给定的输出项。 触发器(52)包含设定输入引线(S)和复位输入引线(R)。 存在于设定输入,复位输入,时钟引脚的信号由PLA内的可编程逻辑产生。 提供了多路复用器(54),其接收触发器(52)的输出数据和构成触发器的输入数据的信号。 当设置和复位输入信号都为真时,多路复用器在多路复用器输出引线(60)上提供数据输入信号。 然而,如果设置和复位输入信号中的任何一个或两者都为假,则多路复用器(54)从多路复用器输出引线(60)上的触发器(52)提供Q输出信号。 复用器输出信号被呈现给三态缓冲器(62),其又驱动输出引脚。
    • 2. 发明授权
    • Health information gathering system
    • 卫生信息采集系统
    • US08738392B2
    • 2014-05-27
    • US10280724
    • 2002-10-24
    • Constance Y. FitzpatrickMark E. Fitzpatrick
    • Constance Y. FitzpatrickMark E. Fitzpatrick
    • G06Q10/00G06Q50/00
    • G06F19/322G06F19/00G06F19/3418G06F19/3475G06Q10/10G06Q50/22G16H10/20G16H10/60G16H15/00
    • A health information gathering system for gathering information from at least one user. The health information gathering system includes a database storing information relating to a user and pertaining to at least two of the areas of information selected from a group consisting of nutritional information, psychological information, occupational information, physical information and personal history information, access to the information stored in the database being controlled by the user. The user can input information pertaining to the at least two areas of information selected from the group consisting of nutritional information, psychological information, occupational information, physical information and personal history information into the database, and the user can retrieve information from the database.
    • 一种用于从至少一个用户收集信息的健康信息收集系统。 健康信息收集系统包括存储与用户有关的信息的数据库,并且涉及从由营养信息,心理信息,职业信息,身体信息和个人历史信息组成的组中选择的至少两个信息区域,访问 存储在数据库中的由用户控制的信息。 用户可以将从包括营养信息,心理信息,职业信息,物理信息和个人历史信息的组中选择的至少两个信息区域的信息输入到数据库中,并且用户可以从数据库中检索信息。
    • 3. 发明授权
    • Phase-locked loop with clamped voltage-controlled oscillator
    • 钳位电压控制振荡器的锁相环
    • US5072195A
    • 1991-12-10
    • US505851
    • 1990-04-05
    • Andrew C. GrahamMark E. FitzpatrickWei Chen
    • Andrew C. GrahamMark E. FitzpatrickWei Chen
    • H03L7/07H03L7/10
    • H03L7/0805H03L7/07H03L7/10
    • A phase-locked loop responsive to both phase and frequency difference between the incoming signal and the feedback signal is provided. Using a reference signal, this phase-locked loop accepts a wide range of frequencies similar to a phase-locked loop having a phase frequency detector, and also achieves the noise performance of a phase-locked loop having only a simple phase detector. In one embodiment, the phase-locked loop is a combination including first and second phase-locked loops. The reference signal is provided to the first phase-locked loop, which includes a phase frequency detector. This first phase-locked loop is used to control a second phase-locked loop, which includes a phase detector. A voltage clamp can also be provided to enhance the ability to lock a signal among several signals, or from a noisy background.
    • 提供响应于输入和反馈信号之间的相位和频率差的锁相环。 使用参考信号,该锁相环接收类似于具有相位检波器的锁相环的宽范围的请求,并且还实现了仅具有简单相位检测器的锁相环的噪声性能。 在一个实施例中,锁相环是包括第一和第二锁相环的组合。 参考信号被提供给包括相位频率检测器的第一锁相环。 该第一锁相环用于控制包括相位检测器的第二锁相环。 还可以提供电压钳,以增强在几个信号之间或从嘈杂背景中锁定信号的能力。
    • 7. 发明授权
    • Logic circuit resistant to errors due to supply fluctuations
    • 逻辑电路抵抗由于电源波动引起的错误
    • US4871931A
    • 1989-10-03
    • US115147
    • 1987-10-30
    • Mark E. FitzpatrickGary R. GouldsberryYat-Sum ChanRichard F. Pang
    • Mark E. FitzpatrickGary R. GouldsberryYat-Sum ChanRichard F. Pang
    • H03K19/003
    • H03K19/00384
    • An improved logic circuit is disclosed, of the type in which one or more input signals, generated by one or more input signal generator circuits, are referenced to a threshold voltage, determined by a threshold voltage generator circuit, to determine whether said one or more input signals are in a high or low state. In this improved logic circuit, the time constants of the input signal generator circuits are matched with those of the threshold voltage generator circuit so that any power supply perturbations commonly applied to the input signal generator circuits and threshold voltage generator circuit, such as due to the switching on or off of output loads, will result in these circuits having substantially identical frequency responses and amplitude versus time responses.
    • 公开了一种改进的逻辑电路,其中由一个或多个输入信号发生器电路产生的一个或多个输入信号参考由阈值电压发生器电路确定的阈值电压,以确定所述一个或多个 输入信号处于高电平或低电平状态。 在这种改进的逻辑电路中,输入信号发生器电路的时间常数与阈值电压发生器电路的时间常数相匹配,使得通常施加到输入信号发生器电路和阈值电压发生器电路的任何电源扰动,例如由于 导通或关断输出负载,将导致这些电路具有基本相同的频率响应和振幅对时间响应。
    • 8. 发明授权
    • FET constant reference voltage generator
    • FET恒定参考电压发生器
    • US4868416A
    • 1989-09-19
    • US133115
    • 1987-12-15
    • Mark E. FitzpatrickGary R. Gouldsberry
    • Mark E. FitzpatrickGary R. Gouldsberry
    • G05F3/24
    • G05F3/24
    • The present invention includes circuitry wherein a pair of voltage supply terminals are included, with a first current source connected to one voltage supply terminal and a second current source connected to the other voltage supply terminal. A load connects the first and second currect sources. A field effect transistor has a first current handling terminal connected between the first current source and load, a second current handling terminal connected to the other voltage supply terminal, and a current control terminal connected between the load and the second current source. The second current source is of the type wherein the current thereacross is substantially independent of changes in voltage thereacross.
    • 本发明包括其中包括一对电压源端子的电路,其中第一电流源连接到一个电压源端子和连接到另一个电压源端子的第二电流源。 负载连接第一和第二弯曲源。 场效应晶体管具有连接在第一电流源和负载之间的第一电流处理端子,连接到另一个电压源端子的第二电流处理端子和连接在负载和第二电流源之间的电流控制端子。 第二电流源是其中的电流基本上独立于其上的电压变化的类型。