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1. 发明授权

US4684830A Output circuit for a programmable logic array 失效
标题翻译：可编程逻辑阵列的输出电路
公开(公告)号：US4684830A
公开(公告)日：1987-08-04
申请号：US715214
申请日：1985-03-22
申请人： Cyrus Tsui , Andrew K. L. Chan , Albert Chan , Mark E. Fitzpatrick , Zahid Ansari
发明人： Cyrus Tsui , Andrew K. L. Chan , Albert Chan , Mark E. Fitzpatrick , Zahid Ansari
IPC分类号： H03K19/177 , H03K19/20
CPC分类号： H03K19/17716
摘要： An output circuit (50) is provided for a programmable logic array (PLA) integrated circuit. The output circuit (50) includes a flip flop (52) which stores a given output term from the array. The flip flop (52) contains a set input lead (S) and a reset input lead (R). The signals present at the set input, reset input, the clock leads are generated by programmable logic within the PLA. A multiplexer (54) is provided which receives the output data of the flip flop (52) and the signal constituting the input data for the flip flop. The multiplexer provides the data input signal on the multiplexer output lead (60) when both the set and reset input signals are true. However, if either or both the set and reset input signals are false, then the multiplexer (54) provides the Q output signal from the flip flop (52) on the multiplexer output lead (60). The multiplexer output signal is presented to a three-state buffer (62) which in turn drives an output pin.
摘要翻译：为可编程逻辑阵列（PLA）集成电路提供输出电路（50）。输出电路（50）包括一个触发器（52），该触发器存储来自阵列的给定的输出项。触发器（52）包含设定输入引线（S）和复位输入引线（R）。存在于设定输入，复位输入，时钟引脚的信号由PLA内的可编程逻辑产生。提供了多路复用器（54），其接收触发器（52）的输出数据和构成触发器的输入数据的信号。当设置和复位输入信号都为真时，多路复用器在多路复用器输出引线（60）上提供数据输入信号。然而，如果设置和复位输入信号中的任何一个或两者都为假，则多路复用器（54）从多路复用器输出引线（60）上的触发器（52）提供Q输出信号。复用器输出信号被呈现给三态缓冲器（62），其又驱动输出引脚。

2. 发明授权

US4758746A Programmable logic array with added array of gates and added output routing flexibility 失效
标题翻译：可编程逻辑阵列，增加了门阵列，增加了输出布线灵活性
公开(公告)号：US4758746A
公开(公告)日：1988-07-19
申请号：US765038
申请日：1985-08-12
申请人： John Birkner , Hua T. Chua , Andrew K. L. Chan , Albert Chan
发明人： John Birkner , Hua T. Chua , Andrew K. L. Chan , Albert Chan
IPC分类号： G06F7/00 , H03K19/177
CPC分类号： H03K19/17708 , H03K19/17712
摘要： A programmable logic array (100) includes a set of input terms which are programmably coupled to a first set of AND gates (102-1) through 102-66). The output signals from the first set of AND gates are programambly electrically connected to a second set of AND gates (104-1 through 104-66). The second set of programmable AND gates enhances flexibility of design and permits product terms with a larger number of factors to be generated. The output leads from the second set of AND gates are programmably electrically coupled to a first set of OR gates (106-1 through 106-22) which in turn are programably electrically coupled to a second array of OR gate logic (108-1 through 108-10). This also permits greater design flexibility. The output terms from the second set of OR gate logic can then be used to generate the output signals from the programmable logic array (100). In addition, a bus (110) is programmably electrically coupled to each of the output signals from the second OR logic array and the output signals (O.sub.1 through O.sub.10) of the PLA. Because of this, different output terms can be routed to different output pins thus permitting the designer to select his pin out independently of the availability of gate within specific parts of the array.
摘要翻译：可编程逻辑阵列（100）包括可编程地耦合到第一组与门（102-1）至102-66的一组输入项。来自第一组与门的输出信号被编程电连接到第二组与门（104-1至104-66）。第二组可编程AND门增强了设计的灵活性，并允许产生具有更多因素的产品术语。来自第二组“与”门的输出引脚可编程地电耦合到第一组或门（106-1至106-22），该组门依次可编程地电耦合到或门逻辑（108-1至 108-10）。这也允许更大的设计灵活性。然后可以使用来自第二组OR门逻辑的输出项来产生来自可编程逻辑阵列（100）的输出信号。此外，总线（110）可编程地电耦合到来自PLA的第二OR逻辑阵列和输出信号（O1至O10）的每个输出信号。因此，不同的输出项可以被路由到不同的输出引脚，从而允许设计者独立于阵列的特定部分内的门的可用性来选择他的引脚。

3. 发明授权

US5544070A Programmed programmable device and method for programming antifuses of a programmable device 失效
标题翻译：用于编程可编程器件的反熔丝的编程可编程器件和方法
公开(公告)号：US5544070A
公开(公告)日：1996-08-06
申请号：US937331
申请日：1992-08-27
申请人： William D. Cox , Andrew K. L. Chan , Richard J. Wong , James M. Apland , Kathryn E. Gordon
发明人： William D. Cox , Andrew K. L. Chan , Richard J. Wong , James M. Apland , Kathryn E. Gordon
IPC分类号： G11C17/16 , G11C17/18 , H01L23/525 , H03K19/177
CPC分类号： H03K19/17764 , G11C17/16 , G11C17/18 , H01L23/5252 , H03K19/17704 , H03K19/1778 , H01L2924/0002 , H01L2924/3011
摘要： A programmable device comprises a first antifuse programmed with a first programming method and a second antifuse programmed with a second programming method, whereby an actual operating current flowing through the second antifuse exceeds a maximum permissible operating current of the first antifuse but does not exceed a maximum permissible operating current of the second antifuse, whereby an actual operating current flowing through the first antifuse does not exceed the maximum permissible operating current of the first antifuse, and whereby an actual operating current flowing through the second antifuse does not exceed the maximum permissible operating current of the second antifuse. By allowing the use of a programming method on some antifuses which would not be adequate for the programming of other antifuses, the realization of user-specific circuits in field programmable devices is facilitated and the reliability of user-specific circuits realized in field programmable devices is enhanced.
摘要翻译：可编程器件包括用第一编程方法编程的第一反熔丝和用第二编程方法编程的第二反熔丝，由此流过第二反熔丝的实际工作电流超过第一反熔丝的最大允许工作电流但不超过最大值第二反熔丝的允许工作电流，由此流过第一反熔丝的实际工作电流不超过第一反熔丝的最大允许工作电流，由此流过第二反熔丝的实际工作电流不超过最大允许工作电流的第二个反熔丝。通过允许在一些反熔丝上使用编程方法来编程其他抗反熔丝，对于现场可编程器件中的用户特定电路的实现是有利的，并且在现场可编程器件中实现的用户特定电路的可靠性是增强。

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