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1. 发明授权

US5627717A Electronic processing unit, and circuit breaker including such a unit 失效
标题翻译：电子处理单元和包括这种单元的断路器
公开(公告)号：US5627717A
公开(公告)日：1997-05-06
申请号：US366149
申请日：1994-12-28
申请人： Howard B. Pein , Gregory T. Divincenzo , Paulo Caldiera , Wen-Jian Gu , Stephen L. Wong
发明人： Howard B. Pein , Gregory T. Divincenzo , Paulo Caldiera , Wen-Jian Gu , Stephen L. Wong
IPC分类号： H02H3/093 , H02H3/00
CPC分类号： H02H3/0935
摘要： Digital processing of current signals allows close matching of arbitrary time delay curves for a circuit breaker. An analog signal proportional to the current is sampled and digitized. Digital samples, with or without further processing, are used to select increment values from a look-up table for accumulation in a counter. The counter is decremented periodically to simulate cooling of the circuit being protected. The values in the look-up table are determined according to the desired time delay curve. Processing of the digital samples may include squaring samples, accumulating the squared values to form a subtotal which is compared with an instantaneous trip threshold, accumulating the subtotals for a time period equal to half a cycle of AC line voltage, taking the square root of the accumulated subtotals, and using that square root as the address for looking up the increment value.
摘要翻译：电流信号的数字处理允许断路器的任意时间延迟曲线的紧密匹配。与电流成比例的模拟信号被采样和数字化。使用或不进行进一步处理的数字样本用于从查找表中选择增量值以累积在计数器中。计数器周期性地递减，以模拟被保护电路的冷却。查找表中的值根据所需的时间延迟曲线确定。数字样本的处理可以包括平方样本，累积平方值以形成小计，其与瞬时跳闸阈值进行比较，将小计累加等于AC线电压的一半周期的时间段，取平均根累积小计，并使用该平方根作为查找增量值的地址。

2. 发明授权

US5418673A Control electrode disable circuit for power transistor 失效
标题翻译：功率晶体管的控制电极禁用电路
公开(公告)号：US5418673A
公开(公告)日：1995-05-23
申请号：US989628
申请日：1992-12-14
申请人： Stephen L. Wong
发明人： Stephen L. Wong
IPC分类号： G05F1/56 , H02H7/00 , H03K17/06 , H03K17/0812
CPC分类号： H03K17/08122 , H03K17/063
摘要： Power transistors used as high-side power switches are typically subjected to a variety of potentially destructive conditions, such as loss of bias current or loss of a ground connection in associated control circuitry. In order to protect the power transistor upon occurrence of such a potentially destructive condition, a control electrode disable circuit is provided to ensure that the power transistor will be turned off upon the occurrence of such a condition, or when the control circuits are deliberately turned off or placed in a standby mode. Turn-off of the power transistor is ensured by shunting a disable transistor across the input of the power transistor, and providing a disable circuit for activating the disable transistor in the event of loss of bias or loss of ground in the control circuitry. Reliable activation of the disable transistor is ensured by a bootstrap capacitor circuit in the disable circuit.
摘要翻译：用作高端功率开关的功率晶体管通常经受各种潜在的破坏性条件，例如相关控制电路中偏置电流的损失或接地连接的损耗。为了在发生这种潜在的破坏性条件时保护功率晶体管，提供控制电极禁用电路以确保功率晶体管在发生这种状态时将被关闭，或者当控制电路故意关闭时或置于待机模式。通过在功率晶体管的输入端分流禁用晶体管来确保功率晶体管的关断，并且在控制电路中的偏置或接地损耗损失的情况下提供用于激活禁用晶体管的禁用电路。禁用晶体管的可靠激活通过禁用电路中的自举电容电路确保。

3. 发明授权

US5365198A Wideband amplifier circuit using npn transistors 失效
标题翻译：宽带放大器电路采用npn晶体管
公开(公告)号：US5365198A
公开(公告)日：1994-11-15
申请号：US125995
申请日：1993-09-23
申请人： Stephen L. Wong
发明人： Stephen L. Wong
IPC分类号： H03F3/343 , H03F3/04
CPC分类号： H03F3/343
摘要： A wideband amplifier circuit provides high current gain and a wide bandwidth by employing only npn transistors, which have better high-frequency characteristics than those of pnp transistors, in the signal path. Wideband current amplification is achieved using npn transistors in a current-mirror configuration, with base-emitter voltage matching to permit the current gain to be easily set as a function of transistor area. The wideband amplifier circuit can also be used in a differential wideband amplifier configuration to obtain a combination of high current gain, wide bandwidth and wide output swing not obtainable with conventional differential amplifiers.
摘要翻译：宽带放大器电路通过在信号路径中仅采用具有比pnp晶体管更高的高频特性的npn晶体管来提供高电流增益和宽带宽。使用电流镜配置中的npn晶体管实现宽带电流放大，基极 - 发射极电压匹配允许电流增益容易地设置为晶体管面积的函数。宽带放大器电路还可以用于差分宽带放大器配置，以获得高电流增益，宽带宽和宽输出摆幅的组合，不能用传统的差分放大器获得。

4. 发明授权

US4893212A Protection of power integrated circuits against load voltage surges 失效
标题翻译：保护功率集成电路免受负载电压浪涌
公开(公告)号：US4893212A
公开(公告)日：1990-01-09
申请号：US288062
申请日：1988-12-20
申请人： Stephen L. Wong , Satyendranath Mukherjee
发明人： Stephen L. Wong , Satyendranath Mukherjee
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8234 , H01L27/02 , H01L27/088 , H01L29/78 , H03K17/0812 , H03K17/0814
CPC分类号： H01L27/0251 , H03K17/08122 , H03K17/08142
摘要： A power integrated-circuit device is protected against load voltage surges. This is done by providing an alternate current-carrying path that is activated only in response to the occurrence of such surges. This alternate path is independent of and separate from the connection that extends between the device and its power supply source. In addition, circuitry is connected to the device to limit the portion of the surge voltage that can appear across critical elements of the device.

5. 发明授权

US4525679A High gain amplifying stage by output conductance cancellation 失效
标题翻译：高增益放大级通过输出电导取消
公开(公告)号：US4525679A
公开(公告)日：1985-06-25
申请号：US452511
申请日：1982-12-23
申请人： Stephen L. Wong , Clement A. T. Salama
发明人： Stephen L. Wong , Clement A. T. Salama
IPC分类号： H03F3/345 , H03K3/354 , H03F3/16 , H03F1/38 , H03G3/18
CPC分类号： H03F3/345 , H03K3/354
摘要： A Metal-Oxide Semiconductor (MOS) high gain amplifying stage which overcomes the inherently low transconductance, gm, of MOS transistors is described. This is achieved by using a specially configured load transistor in combination with a driver transistor. The load transistor is provided, by means of positive feedback, with a current generator which is dependent on the output voltage of the stage and has an effective negative output conductance. The positive feedback is achieved by connecting an appropriate attenuation stage between the output and the input of the load transistor. By the cancellation of output conductances between the driver and load transistors, a near infinite voltage gain can be achieved despite resistive loading at the output of the amplifier. The MOS amplifying stage has application in amplifiers, comparators and oscillators. A complementary metal-oxide-semiconductor (CMOS) implementation has been realized but the principle is equally applicable to single channel (NMOS or PMOS) MOS technology.
摘要翻译：描述了克服MOS晶体管的固有低跨导gm的金属氧化物半导体（MOS）高增益放大级。这是通过使用专门配置的负载晶体管与驱动晶体管结合来实现的。负载晶体管通过正反馈与电流发生器一起提供，电流发生器取决于载物台的输出电压并具有有效的负输出电导。正反馈通过连接负载晶体管的输出和输入之间的适当衰减级来实现。通过消除驱动器和负载晶体管之间的输出电导，尽管在放大器的输出端有电阻负载，但是可以实现接近无限的电压增益。 MOS放大级可用于放大器，比较器和振荡器。已经实现了互补金属氧化物半导体（CMOS）实现，但其原理同样适用于单通道（NMOS或PMOS）MOS技术。

6. 发明授权

US6037720A Level shifter 失效
标题翻译：电平移位器
公开(公告)号：US6037720A
公开(公告)日：2000-03-14
申请号：US177964
申请日：1998-10-23
申请人： Stephen L. Wong , Paul Veldman , Eugene J. De Mol
发明人： Stephen L. Wong , Paul Veldman , Eugene J. De Mol
IPC分类号： H02M7/12 , G05F1/00 , H02M1/08 , H03K17/06 , H03K17/687 , H03K17/695
CPC分类号： H03K17/6871 , H03K17/163 , H03K19/017509 , H05B41/2828 , H03K17/162 , Y02B20/186
摘要： A switched bridge circuit includes a low voltage to high voltage interface which selectively controls an input to a high side switch. A controller compares the voltage across the interface, the state of the high side switch, and the output of the circuit. If hard switching is detected by the controller, it latches the voltage across the interface thus keeping the high side switch on to allow the hard switching to occur. If soft switching is detected, the high side switch is kept off. A source follower is used to drive the high side switch so that the circuit output follows the interface output thereby avoiding oscillation. A falling edge detector for the output of the circuit uses the inherent parasitic capacitance of a high voltage device which also forms a bootstrap diode. When the output drops, the parasitic capacitance feeds a resistance which causes a driver to actuate. A second falling edge detector uses the inherent parasitic capacitance of the level shifter switch which is another high voltage device. When the output drops, the parasitic capacitance turns on a switch. A rising edge detector also uses the inherent capacitance of the low voltage to high voltage interface. A switch is coupled to the circuit output and the low voltage to high voltage interface. When the circuit output rises, the switch actuates.
摘要翻译：开关桥式电路包括低电压至高压接口，其选择性地控制对高侧开关的输入。控制器比较接口电压，高侧开关的状态和电路的输出。如果控制器检测到硬切换，则它锁存接口上的电压，从而保持高侧开关接通，以允许发生硬切换。如果检测到软开关，则高侧开关保持关闭。源极跟随器用于驱动高侧开关，使得电路输出跟随接口输出，从而避免振荡。用于电路输出的下降沿检测器使用也形成自举二极管的高压器件的固有寄生电容。当输出下降时，寄生电容提供一个使驱动器致动的电阻。第二个下降沿检测器使用另一个高压器件的电平转换开关的固有寄生电容。当输出下降时，寄生电容打开开关。上升沿检测器还使用低电压至高压接口的固有电容。开关耦合到电路输出和低电压到高压接口。当电路输出上升时，开关动作。

7. 发明授权

US5844443A Linear high-frequency amplifier with high input impedance and high power efficiency 失效
标题翻译：具有高输入阻抗和高功率效率的线性高频放大器
公开(公告)号：US5844443A
公开(公告)日：1998-12-01
申请号：US762876
申请日：1996-12-12
申请人： Stephen L. Wong
发明人： Stephen L. Wong
IPC分类号： H03F1/32 , H03F1/02 , H03F1/30 , H03F3/30 , H03F3/26
CPC分类号： H03F1/302 , H03F1/307
摘要： A high-frequency power amplifier circuit offers the advantages of high input impedance, good linearity, high power efficiency and accurate bias current control in a compact and economical circuit configuration. The amplifier includes a single-ended output stage driven by a symmetrical push-pull emitter follower stage with both active pull-down and active pull-up capability. The emitter follower stage is driven by an active phase-splitter stage, with bias current for the phase-splitter stage and subsequent stages being provided by a bias-current control stage which is directly connected to the phase splitter stage. A linear voltage-to-current converter stage receives a high-frequency input voltage and provides a high-frequency current signal to the input terminal of the bias-current control stage that controls the current in the output stage.
摘要翻译：高频功率放大器电路在紧凑且经济的电路配置中具有高输入阻抗，良好的线性度，高功率效率和精确的偏置电流控制的优点。放大器包括由对称推挽射极跟随器级驱动的单端输出级，具有有源下拉和有源上拉功能。射极跟随器级由有源分相器级驱动，用于分相器级的偏置电流，并且后续级由直流连接到分相器级的偏置电流控制级提供。线性电压 - 电流转换器级接收高频输入电压，并向控制输出级中的电流的偏置电流控制级的输入端提供高频电流信号。

8. 发明授权

US5719521A Integrated half-bridge timing control circuit 失效
标题翻译：集成半桥定时控制电路
公开(公告)号：US5719521A
公开(公告)日：1998-02-17
申请号：US741163
申请日：1996-10-29
申请人： Stephen L. Wong
发明人： Stephen L. Wong
IPC分类号： H03K17/10 , H03K17/06 , H03K17/16 , H03K17/687 , H03K3/00
CPC分类号： H03K17/6871 , H03K17/063
摘要： An integrated half-bridge timing control circuit for driving a half-bridge output stage has high-side and low-side power transistors coupled together at a high-voltage output terminal, and a bistable circuit for generating a high-side timing control waveform. The bistable circuit is driven by two delay circuits, each of which is decoupled from the high-side voltage by an associated interface circuit. The interface circuits are driven by input voltages which are delayed with respect to each other and which are referenced to the low side (ground). In this manner, an integrated half-bridge timing control circuit is obtained which is capable of operating at high frequencies with little power loss, which can be easily integrated, and which is both accurate and easily adjustable in operation.
摘要翻译：用于驱动半桥输出级的集成半桥定时控制电路具有在高电压输出端子耦合在一起的高侧和低侧功率晶体管，以及用于产生高端定时控制波形的双稳态电路。双稳态电路由两个延迟电路驱动，每个延迟电路通过相关的接口电路与高侧电压分离。接口电路由相对于彼此延迟并以低端（接地）参考的输入电压驱动。以这种方式，可以获得能够以很小功率损耗的高频率运行的集成半桥定时控制电路，其可以容易地集成，并且在操作中既准确又容易调节。

9. 发明授权

US5687067A Low noise controller for pulse width modulated converters 失效
标题翻译：用于脉宽调制转换器的低噪声控制器
公开(公告)号：US5687067A
公开(公告)日：1997-11-11
申请号：US453412
申请日：1995-05-30
申请人： Naveed Majid , Stephen L. Wong
发明人： Naveed Majid , Stephen L. Wong
IPC分类号： H02M1/12 , H02M3/335 , H03K17/16 , H02M7/5395
CPC分类号： H03K17/166 , H02M1/12 , H02M3/33507 , H02M1/44
摘要： A controller for supplying a switching drive voltage signal to a semiconductor power switch includes a wave-shaper circuit that generates a piece wise linear (PWL) waveform that slows the rate of change of the drive voltage supplied to the control electrode of the semiconductor power switch. As a result, the radiated electromagnetic interference generated by the apparatus can be appreciably reduced.
摘要翻译：用于向半导体功率开关提供开关驱动电压信号的控制器包括波形整形器电路，其生成分段线性（PWL）波形，其减慢提供给半导体功率开关的控制电极的驱动电压的变化率。结果，可以显着地减少由该装置产生的辐射电磁干扰。

10. 发明授权

US5081371A Integrated charge pump circuit with back bias voltage reduction 失效
标题翻译：集成电荷泵电路具有背偏压降
公开(公告)号：US5081371A
公开(公告)日：1992-01-14
申请号：US610191
申请日：1990-11-07
申请人： Stephen L. Wong
发明人： Stephen L. Wong
IPC分类号： H01L21/8234 , G05F3/20 , G11C5/14 , H01L21/822 , H01L27/04 , H01L27/088 , H02M3/07 , H03K17/06 , H03K17/10
CPC分类号： G11C5/145 , G05F3/205 , H02M3/073 , H03K17/063 , H03K17/102 , H03K2217/0018
摘要： An integrated charge pump circuit with back bias voltage reduction includes one or more diode type voltage-multiplier stages, with each stage having a diode-connected NMOS transistor in place of the conventionally-used p-n junction diode. The transistors are formed within a P-type well, which forms the back gate of each transistor within the well, and the transistor threshold voltages are dependent on the potential of the P-type well. Performance of the charge pump circuit using NMOS transistors is enhanced by the use of a bias circuit which generates a bias voltage as a function of the output voltage generated by the charge pump circuit, and applies this bias voltage to the P-type well to minimize the back-body effects of the NMOS transistors. The bias circuit thus permits the construction of an integrated charge pump circuit with significantly lower MOS diode voltage drops than would otherwise be possible.

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