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    • 4. 发明授权
    • Method for manufacturing a thin film transistor array panel
    • 薄膜晶体管阵列面板的制造方法
    • US08324003B2
    • 2012-12-04
    • US12767667
    • 2010-04-26
    • Hoon KangJin-Ho JuYang-Ho JungJae-Sung Kim
    • Hoon KangJin-Ho JuYang-Ho JungJae-Sung Kim
    • H01L21/311H01L33/44
    • H01L21/76816H01L27/124H01L27/1288
    • A thin film transistor display panel includes gate wiring formed on an insulation substrate and including gate lines, and gate electrodes and gate pads connected to the gate lines; a gate insulation layer covering the gate wiring; a semiconductor pattern formed over the gate insulation layer; data wiring formed over the gate insulation layer or the semiconductor pattern and including source electrodes, drain electrodes, and data pads; a protection layer including a Nega-PR type of organic insulating layer formed all over the semiconductor pattern and the data wiring, wherein the thickness of the Nega-PR type of organic insulating layer in both the gate and data pad regions is smaller than in the other regions; and a pixel electrode connected to the drain electrode. When exposing the Nega-PR type of passivation layer in the pad region during a photolithography process, a photomask having a lattice pattern made of a metal such as Cr that has a line width of less than the resolution of a light exposer is used. Thus, the resulting post-etch height of the passivation layer can be selectively controlled so as to provide reduced effective thickness in the pad regions.
    • 薄膜晶体管显示面板包括形成在绝缘基板上并包括栅极线的栅极布线,以及连接到栅极线的栅电极和栅极焊盘; 覆盖栅极布线的栅极绝缘层; 形成在所述栅极绝缘层上的半导体图案; 数据线形成在栅极绝缘层或半导体图案上,并且包括源电极,漏电极和数据焊盘; 包括形成在整个半导体图案上的Nega-PR型有机绝缘层和数据布线的保护层,其中栅极和数据焊盘区域中的Nega-PR类型的有机绝缘层的厚度小于 其他地区; 以及连接到漏电极的像素电极。 在光刻工艺中,当在焊盘区域中曝光Nega-PR类型的钝化层时,使用具有由诸如Cr之类的金属制成的格子图案的光掩模,该栅极图案的线宽小于曝光器的分辨率。 因此,可以选择性地控制所得到的钝化层的蚀刻后高度,以便在焊盘区域中提供减小的有效厚度。
    • 5. 发明申请
    • METHOD FOR MANUFACTURING A THIN FILM TRANSISTOR ARRAY PANEL
    • 制造薄膜晶体管阵列的方法
    • US20110177639A1
    • 2011-07-21
    • US12767667
    • 2010-04-26
    • Hoon KANGJin-Ho JuYang-Ho JungJae-Sung Kim
    • Hoon KANGJin-Ho JuYang-Ho JungJae-Sung Kim
    • H01L21/768
    • H01L21/76816H01L27/124H01L27/1288
    • A thin film transistor display panel includes gate wiring formed on an insulation substrate and including gate lines, and gate electrodes and gate pads connected to the gate lines; a gate insulation layer covering the gate wiring; a semiconductor pattern formed over the gate insulation layer; data wiring formed over the gate insulation layer or the semiconductor pattern and including source electrodes, drain electrodes, and data pads; a protection layer including a Nega-PR type of organic insulating layer formed all over the semiconductor pattern and the data wiring, wherein the thickness of the Nega-PR type of organic insulating layer in both the gate and data pad regions is smaller than in the other regions; and a pixel electrode connected to the drain electrode. When exposing the Nega-PR type of passivation layer in the pad region during a photolithography process, a photomask having a lattice pattern made of a metal such as Cr that has a line width of less than the resolution of a light exposer is used. Thus, the resulting post-etch height of the passivation layer can be selectively controlled so as to provide reduced effective thickness in the pad regions.
    • 薄膜晶体管显示面板包括形成在绝缘基板上并包括栅极线的栅极布线,以及连接到栅极线的栅电极和栅极焊盘; 覆盖栅极布线的栅极绝缘层; 形成在所述栅极绝缘层上的半导体图案; 数据线形成在栅极绝缘层或半导体图案上,并且包括源电极,漏电极和数据焊盘; 包括形成在整个半导体图案上的Nega-PR型有机绝缘层和数据布线的保护层,其中栅极和数据焊盘区域中的Nega-PR类型的有机绝缘层的厚度小于 其他地区; 以及连接到漏电极的像素电极。 在光刻工艺中,当在焊盘区域中曝光Nega-PR类型的钝化层时,使用具有由诸如Cr之类的金属制成的格子图案的光掩模,该栅极图案的线宽小于曝光器的分辨率。 因此,可以选择性地控制所得到的钝化层的蚀刻后高度,以便在焊盘区域中提供减小的有效厚度。
    • 6. 发明授权
    • Thin film transistor array panel and method for manufacturing the same
    • 薄膜晶体管阵列面板及其制造方法
    • US08501512B2
    • 2013-08-06
    • US12910268
    • 2010-10-22
    • Jae-Sung KimHoon KangYang-Ho Jung
    • Jae-Sung KimHoon KangYang-Ho Jung
    • H01L33/08
    • G02F1/136227G02F1/00H01L27/1248H01L27/1288H01L29/41733
    • A manufacturing method of a thin film transistor array panel includes forming a gate line, forming a gate insulating layer on the gate line, forming a data line including a drain electrode on the gate insulating layer, forming a passivation layer on the gate insulating layer, the data line, and the drain electrode, forming a negative photosensitive organic layer on the passivation layer, heat treating the negative photosensitive organic layer to form an insulating layer including a first portion, and a second portion that is thinner than the first portion, and forming a pixel electrode, a first contact assistant, and a second contact assistant on the insulating layer. The pixel electrode is disposed on the first portion, the first and second contact assistants are disposed on the second portion, and the thickness of the second portion is less than about 1.5 micrometers (μm).
    • 薄膜晶体管阵列面板的制造方法包括形成栅极线,在栅极线上形成栅极绝缘层,在栅极绝缘层上形成包括漏电极的数据线,在栅极绝缘层上形成钝化层, 数据线和漏电极,在钝化层上形成负光敏有机层,对负光敏有机层进行热处理,形成包含第一部分的绝缘层和比第一部分薄的第二部分,以及 在绝缘层上形成像素电极,第一接触辅助件和第二接触辅助件。 像素电极设置在第一部分上,第一和第二接触助剂设置在第二部分上,第二部分的厚度小于约1.5微米(母体)。